NDLI: Energy-aware mapping for tile-based NoC architectures under performance constraints

Content Provider	IEEE Xplore Digital Library
Author	Jingcao Hu Marculescu, R.
Copyright Year	2003
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA (Jingcao Hu; Marculescu, R.)
Abstract	In this paper, we present an algorithm which automatically maps the IPs/cores onto a generic regular Network on Chip (NoC) architecture such that the total communication energy is minimized. At the same time, the performance of the mapped system is guaranteed to satisfy the specified constraints through bandwidth reservation. As the main contribution, we first formulate the problem of energy-aware mapping, in a topological sense, and then propose an efficient branch-and-bound algorithm to solve it. Experimental results show that the proposed algorithm is very fast and robust, and significant energy savings can be achieved. For instance, for a complex video/audio SoC design, on average, 60.4% energy savings have been observed compared to an ad-hoc implementation.
Sponsorship	IEEE Circuits & Syst. Soc. ACM SIGDA IEICE (Inst. Electon., Inf. & Commun. Eng.) IPSJ (Inf. Process. Soc. Japan)
Starting Page	233
Ending Page	239
File Size	746353
Page Count	7
File Format	PDF
ISBN	0780376595
DOI	10.1109/ASPDAC.2003.1195022
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-01-24
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Network-on-a-chip Tiles Computer architecture Digital signal processing chips Integrated circuit interconnections Power system interconnection Routing Wires Design optimization Electronic mail
Content Type	Text
Resource Type	Article

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