NDLI: A frequency separation macromodel for system-level simulation of RF circuits

Content Provider	IEEE Xplore Digital Library
Author	Xin Li Peng Li Yang Xu Dimaggio, R. Pileggi, L.
Copyright Year	2003
Description	Author affiliation: Carnegie Mellon Univ., Pittsburgh, PA, USA (Xin Li; Peng Li; Yang Xu; Dimaggio, R.; Pileggi, L.)
Abstract	In this paper, we propose a frequency-separation methodology to generate system-level macromodels for analog and RF circuits. The proposed macromodels are similar in form to those based on Volterra kernel calculations, but are much simpler in terms of characterization and overall model complexity, and can be derived from existing device models. This simplicity is realized by applying some basic assumptions on the form of the input excitations, and via separation of the nonlinearities from the dynamic behavior. In addition, by further separating the ideal model functionality, this macromodel is applicable to strongly nonlinear components such as mixers. While time-varying Volterra series models have been proposed for mixers with a fixed local oscillation (LO) signal, the proposed frequency separation model is completely general and can capture the variations of the LO input during a system-level simulation. The proposed macromodels are demonstrated in a system-level simulation tool based on Simulink for efficient evaluation of the entire RF system and associated components. A GSM receiver system in 0.25 /spl mu/m CMOS process is used to demonstrate the efficacy of these macromodels in our system-level simulation environment.
Sponsorship	IEEE Circuits & Syst. Soc. ACM SIGDA IEICE (Inst. Electon., Inf. & Commun. Eng.) IPSJ (Inf. Process. Soc. Japan)
Starting Page	891
Ending Page	896
File Size	645426
Page Count	6
File Format	PDF
ISBN	0780376595
DOI	10.1109/ASPDAC.2003.1195143
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-01-24
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit simulation Radio frequency Mathematical model Kernel Time varying systems Integrated circuit noise RF signals Computational modeling Predictive models Semiconductor device modeling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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