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| Content Provider | IEEE Xplore Digital Library | 
|---|---|
| Author | Tao Feng Wang, L.-C. Kwang-Ting Cheng Pandey, M. Abadir, M.S. | 
| Copyright Year | 2003 | 
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA (Tao Feng; Wang, L.-C.; Kwang-Ting Cheng) | 
| Abstract | In the past, symbolic trajectory evaluation (STE) was shown to be effective for verifying individual array blocks. However, when applying STE to verify multiple array blocks together as a single system, the run-time OBDD sizes would often blow up. In this paper, we propose using a "dual-rail" symbolic simulation scheme to facilitate the application of STE proof methodology for verifying array systems. The proposed scheme implicitly partitions a given design into control domain and datapath domain, and symbolic simulation is carried out on both domains. With this scheme, the run-time OBDD sizes during the symbolic simulation for each domain can be limited. We demonstrate the effectiveness of our approach by verifying the memory management unit (MMU) in Motorola high-performance microprocessors. The verification of MMU as a whole was not possible before because of the OBDD size blow-up problem when an ordinary symbolic simulator was used in the STE proof process. | 
| Sponsorship | IEEE Circuits & Syst. Soc. ACM SIGDA IEICE (Inst. Electon., Inf. & Commun. Eng.) IPSJ (Inf. Process. Soc. Japan) | 
| Starting Page | 302 | 
| Ending Page | 307 | 
| File Size | 794304 | 
| Page Count | 6 | 
| File Format | |
| ISBN | 0780376595 | 
| DOI | 10.1109/ASPDAC.2003.1195032 | 
| Language | English | 
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) | 
| Publisher Date | 2003-01-24 | 
| Publisher Place | Japan | 
| Access Restriction | Subscribed | 
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) | 
| Subject Keyword | Encoding Size control Registers Application specific processors Runtime Memory management Optimization Engines Multivalued logic Automatic test pattern generation | 
| Content Type | Text | 
| Resource Type | Article | 
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