NDLI: A CMP solution enabling STT-RAM fabrication using via-less process flow

Content Provider	IEEE Xplore Digital Library
Author	Hassan, S.A. Pakala, M. Okazaki, M. Sin, G.
Copyright Year	2014
Description	Author affiliation: Adv. Technol. & Product Dev., Appl. Mater., Inc., Santa Clara, CA, USA (Hassan, S.A.; Pakala, M.; Okazaki, M.; Sin, G.)
Abstract	As current memory technologies become difficult to fabricate and scaling presents a growing challenge, R&D in Spin Transfer Torque Random Access Memory (STT-RAM) is growing rapidly. However, the complex stack of STT-RAM memory presents unique processing challenges. One of these is chemical mechanical planarization (CMP) of oxide and nitride for via-less top contacts. Unique materials used in STT-RAM fabrication require a selective and uniform planarization process. We evaluate ceria and silica slurries for this STT-RAM CMP process. Our results show that ceria-based slurry enables oxide-to-tantalum polish rate selectivity exceeding 100:1 and uniform planarization across the wafer. Electrical results of a device fabricated at Applied Materials show tunnel magneto-resistance (TMR) of 143% that is less than 10% degradation than the blanket film TMR.
Sponsorship	IEEE Electron Dev. Soc.
Starting Page	428
Ending Page	430
File Size	400098
Page Count	3
File Format	PDF
ISBN	9781479939442
DOI	10.1109/ASMC.2014.6846969
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-05-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Slurries Magnetic tunneling Films Tunneling magnetoresistance Silicon compounds Resistance SST-RAM CMP contact memory
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Realization of Magnetic RAM using Magnetic Tunneling Junction in atomic level

Analysis of STT-RAM cell design with multiple MTJs per access

A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM)

Read disturbance issue for nanoscale STT-MRAM

Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM

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Scalability and design-space analysis of a 1T-1MTJ memory cell

STT-MRAM memory cells with enhanced on/off ratio

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A CMP solution enabling STT-RAM fabrication using via-less process flow

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