NDLI: Accelerator-rich CMPs: From concept to real hardware

Content Provider	IEEE Xplore Digital Library
Author	Yu-Ting Chen Cong, J. Ghodrat, M.A. Huang, M. Chunyue Liu Bingjun Xiao Yi Zou
Copyright Year	2013
Description	Author affiliation: Comput. Sci. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA (Yu-Ting Chen; Cong, J.; Ghodrat, M.A.; Huang, M.; Chunyue Liu; Bingjun Xiao; Yi Zou)
Abstract	Application-specific accelerators provide 10-100× improvement in power efficiency over general-purpose processors. The accelerator-rich architectures are especially promising. This work discusses a prototype of accelerator-rich CMPs (PARC). During our development of PARC in real hardware, we encountered a set of technical challenges and proposed corresponding solutions. First, we provided system IPs that serve a sea of accelerators to transfer data between userspace and accelerator memories without cache overhead. Second, we designed a dedicated interconnect between accelerators and memories to enable memory sharing. Third, we implemented an accelerator manager to virtualize accelerator resources for users. Finally, we developed an automated flow with a number of IP templates and customizable interfaces to a C-based synthesis flow to enable rapid design and update of PARC. We implemented PARC in a Virtex-6 FPGA chip with integration of platform-specific peripherals and booting of unmodified Linux. Experimental results show that PARC can fully exploit the energy benefits of accelerators at little system overhead.
Starting Page	169
Ending Page	176
File Size	472943
Page Count	8
File Format	PDF
ISBN	9781479929870
DOI	10.1109/ICCD.2013.6657039
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Acceleration Data transfer Hardware Field programmable gate arrays System-on-chip Resource management Program processors design automation customizable computing computer architecture prototyping FPGA
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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