NDLI: A private level-1 cache architecture to exploit the latency and capacity tradeoffs in multicores operating at near-threshold voltages

Content Provider	IEEE Xplore Digital Library
Author	Hijaz, F. Qingchuan Shi Khan, O.
Copyright Year	2013
Description	Author affiliation: Univ. of Connecticut, Storrs, CT, USA (Hijaz, F.; Qingchuan Shi; Khan, O.)
Abstract	Near-threshold voltage (NTV) operation is expected to enable up to 10× energy-efficiency for future processors. However, reliable operation below a minimum voltage (Vccmin) cannot be guaranteed. Specifically, SRAM bit-cell error rates are expected to rise steeply since their margins can easily be violated at near-threshold voltages. Multicore processors rely on fast private L1 caches to exploit data locality and achieve high performance. In the presence of high bit-cell error rates, an L1 cache can either sacrifice capacity or incur additional latency to correct the errors. We observe that L1 cache sensitivity to hit latency offers a design tradeoff between capacity and latency. When error rate is high at extreme Vccmin, it is worthwhile incurring additional latency to recover and utilize the additional L1 cache capacity. However, at low error rates, the additional constant latency to recover cache capacity degrades performance. With this tradeoff in mind, we propose a novel private L1 cache architecture that dynamically learns and adapts by either recovering cache capacity at the cost of additional latency overhead, or operate at lower capacity while utilizing the benefits of optimal hit latency. Using simulations of a 64-core multicore, we demonstrate that our adaptive L1 cache architecture performs better than both individual schemes at low and high error rates (i.e., various NTV conditions).
Starting Page	85
Ending Page	92
File Size	535555
Page Count	8
File Format	PDF
ISBN	9781479929870
DOI	10.1109/ICCD.2013.6657029
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multicore processing Error analysis Switches Arrays Random access memory Error correction codes Program processors performance and power efficiency Shared-memory multicore near-threshold voltage
Content Type	Text
Resource Type	Article

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