NDLI: Free ECC: An efficient error protection for compressed last-level caches

Content Provider	IEEE Xplore Digital Library
Author	Long Chen Yanan Cao Zhao Zhang
Copyright Year	2013
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA (Long Chen; Yanan Cao; Zhao Zhang)
Abstract	Cache reliability is increasingly a concern as cache cell dimension shrinks and cache capacity grows. Conventionally, an extra, dedicated storage is appended to cache to store error correcting code. Recently, cache compression schemes have been proposed to increase the effective cache capacity of last-level cache (LLC), for which we found the conventional cache ECC design is inefficient. We propose Free ECC that utilizes the unused fragments in compressed cache design to store ECC. It not only reduces the chip overhead but also improves cache utilization and power efficiency. Additionally, we propose an efficient convergent cache allocation scheme to organize the compressed data blocks more effectively than existing schemes. Our evaluation using SPEC CPU2006 and PARSEC benchmarks shows that the Free ECC design improves cache capacity utilization and power efficiency significantly, with negligible overhead on overall performance. This new design makes compressed cache an increasingly viable choice for processors with requirements of high reliability.
Starting Page	278
Ending Page	285
File Size	788941
Page Count	8
File Format	PDF
ISBN	9781479929870
DOI	10.1109/ICCD.2013.6657054
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Error correction codes Resource management Encoding Organizations Flyback transformers Reliability Compression algorithms reliability cache compression ECC
Content Type	Text
Resource Type	Article

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