NDLI: Hardware algorithm for variable precision multiplication on FPGA

Content Provider	IEEE Xplore Digital Library
Author	Nadjia, A. Mohamed, A. Hamid, B. Mohamed, I. Khadidja, M.
Copyright Year	2009
Description	Author affiliation: CDTA (Centre de Développement des Technologies Avancées), BP 17, Baba Hassen, Alger, Algérie (Nadjia, A.; Hamid, B.; Mohamed, I.; Khadidja, M.) \|\| ESI (Ecole nationale Supérieure d'Informatique), BP 68M Oued Smar, Alger, Algérie (Mohamed, A.)
Abstract	A hardwired algorithm for computing the variable precision multiplication is presented in this paper. The computation method is based on the use of a parallel multiplier of size m to compute the multiplication of two numbers of n×m bits. These numbers are represented in the variable precision floating point format, but in this work only the mantissas are considered; the exponents are easily obtained by adding the exponents of the two operands to be multiplied. In this computing method of multiplication, the partial products are added as soon as they are computed, resulting in the use of the lowest memory for intermediate results storage, (i.e. the size of the result is of 2n×m bits). The Xilinx FPGA circuits, of Virtex-II families and bigger ones, have interesting resources such as embedded multipliers 18×18 bits, memory blocks (SelectRam) and carry chain paths for the carry propagation acceleration and DCM blocks (Digital Clock Manager) to generate and control clocks. These resources have been advantageously used, in the implementation, to reduce the computation delay compared to the solution that uses only FPGA CLBs (Configurable Logic Blocks). Our architecture has been tailored to use these efficient resources and the resulting architecture is dedicated to compute the multiplication of operands of sizes ranging from 1×64 bits to 64× 64 bits with a cycle time of 33 ns.
Starting Page	845
Ending Page	848
File Size	357372
Page Count	4
File Format	PDF
ISBN	9781424438075
DOI	10.1109/AICCSA.2009.5069427
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-10
Publisher Place	Morocco
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Field programmable gate arrays Concurrent computing Clocks Computer architecture Circuits Memory management Acceleration Resource management Delay
Content Type	Text
Resource Type	Article

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