NDLI: A global router on GPU architecture

Content Provider	IEEE Xplore Digital Library
Author	Yiding Han Chakraborty, K. Roy, S.
Copyright Year	2013
Description	Author affiliation: Electr. & Comput. Eng., Utah State Univ., Logan, UT, USA (Yiding Han; Chakraborty, K.; Roy, S.)
Abstract	In the modern VLSI design flow, global router is often utilized to provide fast and accurate congestion analysis for upstream processes to improve the design routability. Global routing parallelization is a good candidate to speedup its runtime performance while delivering very competitive solution quality. In this paper, we first study the cause of insufficient exploitable concurrency of the existing net level concurrency model, which has become a major bottleneck for parallelizing the emerging design problems. Then, we mitigate this limitation with a novel fine grain parallel model, with which a GPU based multi-agent global router is designed. Our experimental results indicate that the parallel model can effectively support the GPU based global router, and deliver stable solutions. The runtime comparison with NCTUgr2 has shown that upto 3.9× speedup is achieved by the GPU based router.
Starting Page	78
Ending Page	84
File Size	162991
Page Count	7
File Format	PDF
ISBN	9781479929870
DOI	10.1109/ICCD.2013.6657028
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Graphics processing units Concurrent computing Topology Benchmark testing Memory management Degradation A* search GPGPU Global Routing
Content Type	Text
Resource Type	Article

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