NDLI: FreshCache: Statically and dynamically exploiting dataless ways

Content Provider	IEEE Xplore Digital Library
Author	Basu, A. Hower, D.R. Hill, M.D. Swift, M.M.
Copyright Year	2013
Description	Author affiliation: Dept. of Comput. Sci., Univ. of Wisconsin-Madison, Madison, WI, USA (Basu, A.; Hower, D.R.; Hill, M.D.; Swift, M.M.)
Abstract	Last level caches (LLCs) account for a substantial fraction of the area and power budget in many modern processors. Two recent trends - dwindling die yield that falls off sharply with larger chips and increasing static power - make a strong case for a fresh look at LLC design. Inclusive caches are particularly interesting because many commercially successful processors use inclusion to ease coherence at a cost of some data being stale or redundant. Prior works have demonstrated that LLC designs could be improved through static (at design time) or dynamic (at runtime) use of “dataless ways”. The static dataless ways removes the data-but not tags-from some cache ways to save energy and area without complicating inclusive-LLC coherence. A dynamic version (dynamic dataless ways) could dynamically turn off data, but not tags, effectively adapting the classic selective cache ways idea to save energy in LLC but not area. We find that (a) all our benchmarks benefit from dataless ways, but (b) the best number of dataless ways varies by workload. Thus, a pure static dataless design leaves energy-saving opportunity on the table, while a pure dynamic dataless design misses area-saving opportunity. To surpass both pure static and dynamic approaches, we develop the FreshCache LLC design that both statically and dynamically exploits dataless ways, including a predictor to adapt the number of dynamic dataless ways as well as detailed cache management policies. Results show that FreshCache saves more energy than static dataless ways alone (e.g., 72% vs. 9% of LLC) and more area by dynamic dataless ways only (e.g., 8% vs. 0% of LLC).
Starting Page	286
Ending Page	293
File Size	1171344
Page Count	8
File Format	PDF
ISBN	9781479929870
DOI	10.1109/ICCD.2013.6657055
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Coherence Degradation Runtime Hardware Monitoring Program processors System-on-chip energy efficiency Last level cache area efficiency
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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FreshCache: Statically and Dynamically Exploiting Dataless Ways

Freshcache: statically and dynamically exploiting dataless ways.

EECache: Exploiting design choices in energy-efficient last-level caches for chip multiprocessors

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POPS: Coherence Protocol Optimization for Both Private and Shared Data

FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion

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FreshCache: Statically and dynamically exploiting dataless ways

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