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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kehan Zhu Saxena, V. Xinyu Wu |
| Copyright Year | 2015 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Boise State Univ., Boise, ID, USA (Kehan Zhu; Saxena, V.; Xinyu Wu) |
| Abstract | A 4-level pulse amplitude modulation (PAM-4) silicon photonic transmitter targeting operation at 25 Gb/s is designed using an electrical-photonic co-design methodology. The prototype consists of an electrical circuit and a photonics circuit, which were designed in 130 nm IBM SiGe BiCMOS process and 130nm IME SOI CMOS process, respectively. Then the two parts will be interfaced via side-by-side wire bonding. The electrical die mainly includes a 12.5 GHz PLL, a full-rate 4-channel uncorrelated $2^{7}$ - 1 pseudo-random binary sequence (PRBS) generator and CML drivers. The photonics die is a 2-segment Mach-Zehnder modulator (MZM) silicon photonics device with thermal tuning feature for PAM-4. Verilog-A model for the MZM entails the system simulation for optical devices together with electrical circuitry using custom IC design tools. A full-rate 4-channel uncorrelated PRBS design using transition matrix method is detailed, in which any two of the 4-channels can be used for providing random binary sequence to drive the two segments of the MZM to generate the PAM-4 signal. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 1166289 |
| Page Count | 4 |
| File Format | |
| e-ISBN | 9781467365581 |
| DOI | 10.1109/MWSCAS.2015.7282203 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-08-02 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Generators Integrated circuit modeling Clocks Silicon photonics Wires Phase locked loops |
| Content Type | Text |
| Resource Type | Article |
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