NDLI: An input pole tuned switching equalization scheme for high-speed serial links

Content Provider	IEEE Xplore Digital Library
Author	Sanquan Song Jian Xu Fengxiang Cai Xin Ma Zibing Yang Becker, M. Tate, L. Byungsub Kim Palermo, S. Bowhill, B.
Copyright Year	2015
Description	Author affiliation: Samsung Display American Lab., San Jose, CA, USA (Sanquan Song) \|\| Dept. of Electron. & Electr. Eng., Pohang Univ. of Sci. & Technol., Pohang, South Korea (Byungsub Kim) \|\| Dept. of Electr. & Comput. Eng., Texas A&M Univ., College Station, TX, USA (Palermo, S.) \|\| MMDC Intel Corp., Hudson, MA, USA (Jian Xu; Fengxiang Cai; Xin Ma; Zibing Yang; Becker, M.; Tate, L.; Bowhill, B.)
Abstract	A novel receiver equalization scheme for high-speed links is described in this paper. By per-bit switching the channel-receiver connection, the channel induced inter-symbol interference (ISI) is compensated by receiver (RX) input pole induced ISI. The polarity of the recovered binary bit is adjusted in digital domain to match the transmitted data. An input pole based two-way interleaved switching equalization circuit is proposed and simulated. In comparison with the conventional FIR filter, it improves the output eye width by 63%. This paper provides a new way of converting a low-pass system into a peaking system for link designs, suitable for a broader range of applications.
Starting Page	1
Ending Page	4
File Size	1107306
Page Count	4
File Format	PDF
e-ISBN	9781467365581
DOI	10.1109/MWSCAS.2015.7282031
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-08-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Filtering theory Resistors Clocks Attenuation CMOS integrated circuits peaking equalization switching equalization high-speed links residue
Content Type	Text
Resource Type	Article

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