NDLI: Real-time VLSI architecture for palm rejection using Wronskian Determinant

Content Provider	IEEE Xplore Digital Library
Author	Baker, A.M. Yingtao Jiang
Copyright Year	2015
Description	Author affiliation: Dept. of the Electr. & Comput. Eng., Univ. of Nevada, Las Vegas, NV, USA (Yingtao Jiang) \|\| Hewlett Packard, Houston, TX, USA (Baker, A.M.)
Abstract	Several Human Interface Technology applications require reliable palm rejection. Palm rejection in upcoming touch or Pad technology has a need of hardware implementation with requirements of low power and small area. This paper introduces a hardware implementation of a real-time palm rejection based on Wronskian Determinant. This detection algorithm offers regularity, low complexity and accuracy as well as robustness against global illumination changes. The proposed architecture is able to process incoming frames on-the-fly, therefore requiring a small amount of memory. The maximum frame rate is 15 fps, however the implementation is flexible enough to allow analysis of less frames if required. Processing unit consist of a basic processing element implemented in pipeline fashion and adder tree to produce final results. The architecture was implemented using a XCV800 FPGA. The power consumption of the whole system is 93 mW.
Starting Page	1
Ending Page	4
File Size	762411
Page Count	4
File Format	PDF
e-ISBN	9781467365581
DOI	10.1109/MWSCAS.2015.7282154
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-08-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Process control Field programmable gate arrays Detectors Image resolution Adders Solids FPGA Wronskian Determinant Palm Rejection
Content Type	Text
Resource Type	Article

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