NDLI: Physical design and implementation of POWER8™ (P8) server class processor

Content Provider	IEEE Xplore Digital Library
Author	Hossain, M. Fluhr, E. Hall, A. Agarwal, V.
Copyright Year	2015
Description	Author affiliation: IBM, Austin, TX, USA (Hossain, M.; Fluhr, E.; Hall, A.; Agarwal, V.)
Abstract	POWER8™ (P8) processor is a 12-core, 649mm2, 4.2B transistor chip fabricated in IBM's 22nm SOI technology with 2.5× socket performance improvement over its 32nm predecessor, POWER7+, driven by big data application and power efficient computing. Highly distributed chip voltage regulator achieves a peak power efficiency of 90.5%. Resonant clock design is used in 13 clock meshes to achieve about 4% power savings for the chip. This chip is built with three thin-oxide transistor Vt for power/performance benefit and one thick-oxide transistor to enable high-voltage circuits. In order to achieve desired performance within the power envelop, P8 is built with 7 input voltages and 15-layers of metals along with the use of pulsed-clock latches. The P8 has 15823 total pads: 5982 power, 7742 ground and 2099 signal. The power/performance complexity, size of the die, along with high operating frequency presented significant challenges to complete the design on an aggressive schedule. Some of the design methodology and implementation innovations in P8 have been presented in this paper, with an emphasis on macro design topologies (custom, array and synthesis), timing methodology, as well as the electrical characterizations performed in the chip bring-up lab.
Starting Page	1
Ending Page	4
File Size	900909
Page Count	4
File Format	PDF
e-ISBN	9781467365581
DOI	10.1109/MWSCAS.2015.7282013
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-08-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Metals Fabrics Algorithm design and analysis Monitoring Ear Logic gates Latches register file LBS Synthesis RLM Data Flow Soft Hierarchy Interior Pin array
Content Type	Text
Resource Type	Article

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