NDLI: Co-design of on-chip antennas and circuits for a UNII band monolithic transceiver

Content Provider	IEEE Xplore Digital Library
Author	Shamim, A. Arsalan, M. Roy, L. Salama, K.N.
Copyright Year	2010
Description	Author affiliation: King Abdullah University of Science & Technology, KSA (Shamim, A.; Salama, K.N.) \|\| Carleton University, Canada (Arsalan, M.; Roy, L.)
Abstract	The surge of highly integrated and multifunction wireless devices has necessitated the designers to think outside the box for solutions that are unconventional. The new trends have provided the impetus for low cost and compact RF System-on-Chip (SoC) approaches [1]. The major advantages of SoC are miniaturization and cost reduction. A major bottleneck to the true realization of monolithic RF SoC transceivers is the implementation of on-chip antennas with circuitry. Though complete integrated transceivers with on-chip antennas have been demonstrated, these designs are generally for high frequencies. Moreover, they either use non-standard CMOS processes or additional fabrication steps to enhance the antenna efficiency, which in turn adds to the cost of the system [2–3]. Another challenge related to the on-chip antennas is the characterization of their radiation properties. Most of the recently reported work (summarized in Table I) shows that very few on-chip antennas are characterized. Our previous work [4], demonstrated a Phase Lock Loop (PLL) based transmitter (TX) with an on-chip antenna. However, the radiation from the on-chip antenna experienced strong interference due to 1) some active circuitry on one side of the chip and 2) the PCB used to mount the chip in the anechoic chamber. This paper presents, for the first time, a complete 5.2 GHz (UNII band) transceiver with separate TX and receiver (RX) antennas. To the author's best knowledge, its size of 3 $mm^{2}$ is the smallest reported for a UNII band transceiver with two on-chip antennas. Both antennas are characterized for their radiation properties through an on-wafer custom measurement setup. The strategy to co-design on-chip antennas with circuits, resultant trade-offs and measurement challenges have also been discussed.
Starting Page	1
Ending Page	4
File Size	1060307
Page Count	4
File Format	PDF
ISBN	9781424449675
ISSN	15223965
DOI	10.1109/APS.2010.5562066
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-07-11
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Antenna measurements System-on-a-chip Antenna radiation patterns Receiving antennas Dipole antennas
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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