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Content Provider | IEEE Xplore Digital Library |
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Author | Yu Cai Seungjune Jeon Ken Mai Kumar, B.V.K.V. |
Copyright Year | 1965 |
Abstract | Low-density parity-check (LDPC) codes offer a promising error correction approach for high-density magnetic recording systems due to their near-Shannon limit error-correcting performance. However, evaluation of LDPC codes at the extremely low bit error rates (BER) required by hard disk drive systems, typically around 10-12 to 10- 15, cannot be carried out on high-performance workstations using conventional Monte Carlo techniques in a tractable amount of time. Even field-programmable gate array (FPGA) emulation platforms take a few weeks to reach BER between 10-11 and 10-12. Thus, we implemented a highly parallel FPGA processing cluster to emulate a perpendicular magnetic recording channel, which enabled us to accelerate the emulation by > 100times over the fastest reported emulation. This increased throughput enabled us to characterize the performance of LDPC code BER down to near 10-14 and investigate its error floor. |
Sponsorship | IEEE Magnetics Society |
Starting Page | 3761 |
Ending Page | 3764 |
Page Count | 4 |
File Size | 395140 |
File Format | |
ISSN | 00189464 |
Volume Number | 45 |
Issue Number | 10 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2009-10-01 |
Publisher Place | U.S.A. |
Access Restriction | One Nation One Subscription (ONOS) |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Field programmable gate arrays Emulation Parity check codes Perpendicular magnetic recording Bit error rate Error correction codes Magnetic recording Hard disks Workstations Monte Carlo methods multicore Error floor field-programmable gate array (FPGA) low-density parity-check (LDPC) code |
Content Type | Text |
Resource Type | Article |
Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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