NDLI: An iterative approximation for the charge-storage capacity of MOS capacitors with an application to DRAM trench capacitor memory cells

Content Provider	IEEE Xplore Digital Library
Author	Perry, R.J. Uyemura, J.P.
Copyright Year	1963
Abstract	An iterative approximation based on the charge-sheet model which calculates the charge-storage capacity of a metal-oxide-semiconductor (MOS) capacitor is presented. The iterative approximation combines the numerical accuracy available from two-dimensional semiconductor device simulations with the computational efficiency normally associated with closed-form solutions. In addition, under certain process and bias conditions, the iterative solution predicts behavior not demonstrated by the closed-form equations, but verified by results obtained from device simulations. The approximation is therefore useful in the design of MOS-based circuits when quick but accurate estimations of charge-storage capacity are required. The iterative approximation is applied to estimate the charge-storage capacity of a variety of dynamic random-access memory (DRAM) trench capacitor cells. Several examples comparing charge-storage capacity approximations obtained from numerical semiconductor device simulations, closed-form solutions, and the proposed iterative approximation are given for inversion-store (IST), diffusion-store (DST), substrate-plate (SPT), and stacked (ST) trench-type DRAM cells. As expected, the iterative solution consistently produces results that compared favorable to the results obtained from numerical device simulations but at a much lower computational cost.
Sponsorship	IEEE Electron Devices Society
Starting Page	2217
Ending Page	2225
Page Count	9
File Size	873339
File Format	PDF
ISSN	00189383
Volume Number	42
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computational modeling Circuit simulation Semiconductor devices Computational efficiency Closed-form solution Random access memory Numerical simulation MOS capacitors Equations Predictive models
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

An analytical threshold-voltage model of trench-isolated MOS devices with nonuniformly doped substrates

An Investigation of the Charge Conservation Problem for MOSFET Circuit Simulation

Extending storage dielectric scaling limit by reoxidizing nitrided NO dielectric for trench DRAM

Early termination refresh to reduce refresh overhead

Dielectrics in MOS devices, DRAM capacitors, and inter-metal isolation

A Novel 4.5$hbox{F}^{2}$ Capacitorless Semiconductor Memory Device

Built-in parasitic-diode-based charge injection technique enhancing data retention of gain cell DRAM

A 64 Kbit MOS dynamic RAM with novel memory capacitor

A 1-Mbit CMOS dynamic RAM with design-for test functions

An iterative approximation for the charge-storage capacity of MOS capacitors with an application to DRAM trench capacitor memory cells

Similar Documents

An analytical threshold-voltage model of trench-isolated MOS devices with nonuniformly doped substrates

An Investigation of the Charge Conservation Problem for MOSFET Circuit Simulation

Extending storage dielectric scaling limit by reoxidizing nitrided NO dielectric for trench DRAM

Early termination refresh to reduce refresh overhead

Dielectrics in MOS devices, DRAM capacitors, and inter-metal isolation

A Novel 4.5$hbox{F}^{2}$ Capacitorless Semiconductor Memory Device

Built-in parasitic-diode-based charge injection technique enhancing data retention of gain cell DRAM

A 64 Kbit MOS dynamic RAM with novel memory capacitor

A 1-Mbit CMOS dynamic RAM with design-for test functions

An iterative approximation for the charge-storage capacity of MOS capacitors with an application to DRAM trench capacitor memory cells