NDLI: Early termination refresh to reduce refresh overhead

Content Provider	IET Digital Library
Author	Lee, M. K. Chung, K. S.
Abstract	Dynamic random access memory (DRAM) is mainly used as the main memory in modern computers. Since data is stored in a memory cell that is composed of a capacitor and a transistor, the cell must be periodically refreshed to prevent data loss due to charge leakage. The refresh operation dissipates energy and degrades system performance. Existing DRAM devices determine the refresh interval based on the retention time of the weakest memory cell. However, most DRAM memory cells retain data much longer than the weakest cell. In this Letter, the authors propose a refresh method with early termination that stops the refresh operations early before the completion depending on the retention time. To minimise changes in the existing auto-refresh (AR) operation, the proposed early termination refresh (ETR) uses the same refresh granularity as AR, which is a row group, and marks different retention times for each row group in the memory array. While refreshing a row group in a DRAM device, ETR reads the retention time marked in the memory array and stops the refresh operation if the remaining refresh operations are redundant. ETR improves the average system throughput by 3.1% and reduces the refresh power by 65.4% over AR.
Starting Page	142
Ending Page	144
Page Count	3
ISSN	00135194
Volume Number	54
e-ISSN	1350911X
Issue Number	Issue 3, Feb (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/54/3
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2017.3843
Journal	Electronics Letters
Publisher Date	2017-12-18
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Auto-refresh Operation Capacitor Charge Leakage Data Loss DRAM Chips DRAM Device DRAM Memory Cell Dynamic Random Access Memory Early Termination Refresh ETR Memory Array Memory Circuit Refresh Overhead Reduction Semiconductor Storage System Performance Degradation Transistor Weakest Memory Cell
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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