NDLI: Distributed Microarchitectural Protocols in the TRIPS Prototype Processor

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Distributed Microarchitectural Protocols in the TRIPS Prototype Processor

Content Provider	ACM Digital Library
Author	Gulati, Divya Liu, Haiming Nagarajan, Ramadass Desikan, Rajagopalan Keckler, Stephen W. Burger, Doug Hanson, Heather Shivakumar, Premkishore Drolia, Saurabh Gratz, Paul Govindan, M. S. Kim, Changkyu Sharif, Sadia McDonald, Robert Ranganathan, Nitya Sankaralingam, Karthikeyan Sethumadhavan, Simha
Abstract	Growing on-chip wire delays will cause many future microarchitectures to be distributed, in which hardware resources within a single processor become nodes on one or more switched micronetworks. Since large processor cores will require multiple clock cycles to traverse, control must be distributed, not centralized. This paper describes the control protocols in the TRIPS processor, a distributed, tiled microarchitecture that supports dynamic execution. It details each of the five types of reused tiles that compose the processor, the control and data networks that connect them, and the distributed microarchitectural protocols that implement instruction fetch, execution, flush, and commit. We also describe the physical design issues that arose when implementing the microarchitecture in a 170M transistor, 130nm ASIC prototype chip composed of two 16-wide issue distributed processor cores and a distributed 1MB nonuniform (NUCA) on-chip memory system.
Starting Page	480
Ending Page	491
Page Count	12
File Format	PDF
ISBN	0769527329
ISSN	10724451
DOI	10.1109/MICRO.2006.19
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-12-09
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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