NDLI: Virtually Pipelined Network Memory

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A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design

Yield-Aware Cache Architectures

Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware

PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection

Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths

Merging Head and Tail Duplication for Convergent Hyperblock Formation

Data-Dependency Graph Transformations for Superblock Scheduling

Dataflow Predication

Authentication Control Point and Its Implications For Secure Processor Design

Using Branch Correlation to Identify Infeasible Paths for Anomaly Detection

Memory Protection through Dynamic Access Control

LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting Security Attacks

Fairness and Throughput in Switch on Event Multithreading

A Predictive Performance Model for Superscalar Processors

Serialization-Aware Mini-Graphs: Performance with Fewer Resources

Architectural Support for Software Transactional Memory

Virtually Pipelined Network Memory

Fair Queuing Memory Systems

Reunion: Complexity-Effective Multicore Redundancy

Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers

CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs

Support for High-Frequency Streaming in CMPs

Fire-and-Forget: Load/Store Scheduling with No Store Queue at All

NoSQ: Store-Load Communication without a Store Queue

DMDC: Delayed Memory Dependence Checking through Age-Based Filtering

Coherence Ordering for Ring-based Chip Multiprocessors

In-Network Cache Coherence

ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers

An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget

Live, Runtime Phase Monitoring and Prediction on Real Systems with Application to Dynamic Power Management

Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units

Adaptive Caches: Effective Shaping of Cache Behavior to Workloads

Memory Prefetching Using Adaptive Stream Detection

Scalable Cache Miss Handling for High Memory-Level Parallelism

Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches

Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions

ASR: Adaptive Selective Replication for CMP Caches

Managing Distributed, Shared L2 Caches through OS-Level Page Allocation

Die Stacking (3D) Microarchitecture

Distributed Microarchitectural Protocols in the TRIPS Prototype Processor

Leveraging Optical Technology in Future Bus-based Chip Multiprocessors

Mitigating the Impact of Process Variations on Processor Register Files and Execution Units

Author Index

Virtually Pipelined Network Memory

Content Provider	ACM Digital Library
Author	Agrawal, Banit Sherwood, Timothy
Abstract	We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput even under adversarial conditions. We apply this technique to the network processing domain where memory hierarchy design is an increasingly challenging problem as network bandwidth increases. Virtual pipelining provides a simple to analyze programing model of a deep pipeline (deterministic latencies) with a completely different physical implementation (a memory system with banks and probabilistic mapping). This allows designers to effectively decouple the analysis of their algorithms and data structures from the analysis of the memory buses and banks. Unlike specialized hardware customized for a specific data-plane algorithm, our system makes no assumption about the memory access patterns. In the domain of network processors this will be of growing importance as the size of the routing tables, the complexity of the packet classification rules, and the amount of packet buffering required, all continue to grow at a staggering rate. We present a mathematical argument for our system's ability to provably provide bandwidth with high confidence and demonstrate its functionality and area overhead through a synthesizable design. We further show that, even though our scheme is general purpose to support new applications such as packet reassembly, it outperforms the state of the art in specialized packet buffering architectures.
Starting Page	197
Ending Page	207
Page Count	11
File Format	PDF
ISBN	0769527329
ISSN	10724451
DOI	10.1109/MICRO.2006.51
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-12-09
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Virtually Pipelined Network Memory

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Virtually Pipelined Network Memory

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