NDLI: In-Network Cache Coherence

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A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design

Yield-Aware Cache Architectures

Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware

PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection

Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths

Merging Head and Tail Duplication for Convergent Hyperblock Formation

Data-Dependency Graph Transformations for Superblock Scheduling

Dataflow Predication

Authentication Control Point and Its Implications For Secure Processor Design

Using Branch Correlation to Identify Infeasible Paths for Anomaly Detection

Memory Protection through Dynamic Access Control

LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting Security Attacks

Fairness and Throughput in Switch on Event Multithreading

A Predictive Performance Model for Superscalar Processors

Serialization-Aware Mini-Graphs: Performance with Fewer Resources

Architectural Support for Software Transactional Memory

Virtually Pipelined Network Memory

Fair Queuing Memory Systems

Reunion: Complexity-Effective Multicore Redundancy

Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers

CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs

Support for High-Frequency Streaming in CMPs

Fire-and-Forget: Load/Store Scheduling with No Store Queue at All

NoSQ: Store-Load Communication without a Store Queue

DMDC: Delayed Memory Dependence Checking through Age-Based Filtering

Coherence Ordering for Ring-based Chip Multiprocessors

In-Network Cache Coherence

ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers

An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget

Live, Runtime Phase Monitoring and Prediction on Real Systems with Application to Dynamic Power Management

Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units

Adaptive Caches: Effective Shaping of Cache Behavior to Workloads

Memory Prefetching Using Adaptive Stream Detection

Scalable Cache Miss Handling for High Memory-Level Parallelism

Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches

Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions

ASR: Adaptive Selective Replication for CMP Caches

Managing Distributed, Shared L2 Caches through OS-Level Page Allocation

Die Stacking (3D) Microarchitecture

Distributed Microarchitectural Protocols in the TRIPS Prototype Processor

Leveraging Optical Technology in Future Bus-based Chip Multiprocessors

Mitigating the Impact of Process Variations on Processor Register Files and Execution Units

Author Index

In-Network Cache Coherence

Content Provider	ACM Digital Library
Author	Shang, Li Eisley, Noel Peh, Li-Shiuan
Abstract	With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. However, directory-based protocols face well-known problems in delay and scalability. Most current protocol optimizations targeting these problems maintain a firm abstraction of the interconnection network fabric as a communication medium: protocol optimizations consist of endto- end messages between requestor, directory and sharer nodes, while network optimizations separately target lowering communication latency for coherence messages. In this paper, we propose an implementation of the cache coherence protocol within the network, embedding directories within each router node that manage and steer requests towards nearby data copies, enabling in-transit optimization of memory access delay. Simulation results across a range of SPLASH-2 benchmarks demonstrate significant performance improvement and good system scalability, with up to 44.5% and 56% savings in average memory access latency for 16 and 64-node systems, respectively, when compared against the baseline directory cache coherence protocol. Detailed microarchitecture and implementation characterization affirms the low area and delay impact of in-network coherence.
Starting Page	321
Ending Page	332
Page Count	12
File Format	PDF
ISBN	0769527329
ISSN	10724451
DOI	10.1109/MICRO.2006.27
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-12-09
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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An optimized multicore cache coherence design for exploiting communication locality

A distributed directory based cache coherence scheme (1994).

Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence

On limitations of network acceleration

Comparison of significant issues in multicore cache coherence

A composite and scalable cache coherence protocol for large scale CMPs

Proximity coherence for chip multiprocessors

A distributed directory cache coherence scheme and its effects on network performance (1995).

Measuring and characterizing cache coherence traffic.

In-Network Cache Coherence

Similar Documents

An optimized multicore cache coherence design for exploiting communication locality

A distributed directory based cache coherence scheme (1994).

Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence

On limitations of network acceleration

Comparison of significant issues in multicore cache coherence

A composite and scalable cache coherence protocol for large scale CMPs

Proximity coherence for chip multiprocessors

A distributed directory cache coherence scheme and its effects on network performance (1995).

Measuring and characterizing cache coherence traffic.

In-Network Cache Coherence