NDLI: ASR: Adaptive Selective Replication for CMP Caches

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A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design

Yield-Aware Cache Architectures

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PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection

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Merging Head and Tail Duplication for Convergent Hyperblock Formation

Data-Dependency Graph Transformations for Superblock Scheduling

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Authentication Control Point and Its Implications For Secure Processor Design

Using Branch Correlation to Identify Infeasible Paths for Anomaly Detection

Memory Protection through Dynamic Access Control

LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting Security Attacks

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Serialization-Aware Mini-Graphs: Performance with Fewer Resources

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Fair Queuing Memory Systems

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Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers

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Support for High-Frequency Streaming in CMPs

Fire-and-Forget: Load/Store Scheduling with No Store Queue at All

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Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches

Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions

ASR: Adaptive Selective Replication for CMP Caches

Managing Distributed, Shared L2 Caches through OS-Level Page Allocation

Die Stacking (3D) Microarchitecture

Distributed Microarchitectural Protocols in the TRIPS Prototype Processor

Leveraging Optical Technology in Future Bus-based Chip Multiprocessors

Mitigating the Impact of Process Variations on Processor Register Files and Execution Units

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ASR: Adaptive Selective Replication for CMP Caches

Content Provider	ACM Digital Library
Author	Marty, Michael R. Wood, David A. Beckmann, Bradford M.
Abstract	The large working sets of commercial and scientific workloads stress the L2 caches of Chip Multiprocessors (CMPs). Some CMPs use a shared L2 cache to maximize the on-chip cache capacity and minimize off-chip misses. Others use private L2 caches, replicating data to limit the delay due to global wires and minimize cache access time. Recent hybrid proposals use selective replication to balance latency and capacity, but their static replication rules result in performance degradation for some combinations of workloads and system configurations. This paper proposes Adaptive Selective Replication (ASR), a mechanism that dynamically monitors workload behavior to control replication. ASR replicates cache blocks only when it estimates the benefit of replication (lower L2 hit latency) exceeds the cost (more L2 misses). Full-system simulations of 8-processor CMPs show that ASR provides robust performance: improving performance by as much as 29% versus shared caches, 19% versus private caches, and 12% versus CMP-NuRapid [9] and Victim Replication [41]. Furthermore, while ASR does not improve the performance of all workloads, it provides performance stability by always performing at least comparably to the best alternative including Cooperative Caching [8].
Starting Page	443
Ending Page	454
Page Count	12
File Format	PDF
ISBN	0769527329
ISSN	10724451
DOI	10.1109/MICRO.2006.10
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-12-09
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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ASR: Adaptive Selective Replication for CMP Caches

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ASR: Adaptive Selective Replication for CMP Caches

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