NDLI: Die Stacking (3D) Microarchitecture

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Die Stacking (3D) Microarchitecture

Distributed Microarchitectural Protocols in the TRIPS Prototype Processor

Leveraging Optical Technology in Future Bus-based Chip Multiprocessors

Mitigating the Impact of Process Variations on Processor Register Files and Execution Units

Die Stacking (3D) Microarchitecture

Content Provider	ACM Digital Library
Author	McCaule, Don Webb, Clair Nelson, Donald W. Pantuso, Daniel Rupley, Jeff Morrow, Pat DeVale, John Brekelbaum, Ned Shen, John Black, Bryan Annavaram, Murali Reed, Paul Jiang, Lei Loh, Gabriel H. Shankar, Sadasivan
Abstract	3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die stacking is a significant reduction of interconnect both within a die and across dies in a system. For instance, blocks within a microprocessor can be placed vertically on multiple die to reduce block to block wire distance, latency, and power. Disparate Si technologies can also be combined in a 3D die stack, such as DRAM stacked on a CPU, resulting in lower power higher BW and lower latency interfaces, without concern for technology integration into a single process flow. 3D has the potential to change processor design constraints by providing substantial power and performance benefits. Despite the promising advantages of 3D, there is significant concern for thermal impact. In this research, we study the performance advantages and thermal challenges of two forms of die stacking: Stacking a large DRAM or SRAM cache on a microprocessor and dividing a traditional microarchitecture between two die in a stack Results: It is shown that a 32MB 3D stacked DRAM cache can reduce the cycles per memory access of a twothreaded RMS benchmark on average by 13% and as much as 55% while increasing the peak temperature by a negligible 0.08ºC. Off-die BW and power are also reduced by 66% on average. It is also shown that a 3D floorplan of a high performance microprocessor can simultaneously reduce power 15% and increase performance 15% with a small 14ºC increase in peak temperature. Voltage scaling can reach neutral thermals with a simultaneous 34% power reduction and 8% performance improvement.
Starting Page	469
Ending Page	479
Page Count	11
File Format	PDF
ISBN	0769527329
ISSN	10724451
DOI	10.1109/MICRO.2006.18
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-12-09
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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