NDLI: Yield-Aware Cache Architectures

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A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design

Yield-Aware Cache Architectures

Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware

PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection

Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths

Merging Head and Tail Duplication for Convergent Hyperblock Formation

Data-Dependency Graph Transformations for Superblock Scheduling

Dataflow Predication

Authentication Control Point and Its Implications For Secure Processor Design

Using Branch Correlation to Identify Infeasible Paths for Anomaly Detection

Memory Protection through Dynamic Access Control

LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting Security Attacks

Fairness and Throughput in Switch on Event Multithreading

A Predictive Performance Model for Superscalar Processors

Serialization-Aware Mini-Graphs: Performance with Fewer Resources

Architectural Support for Software Transactional Memory

Virtually Pipelined Network Memory

Fair Queuing Memory Systems

Reunion: Complexity-Effective Multicore Redundancy

Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers

CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs

Support for High-Frequency Streaming in CMPs

Fire-and-Forget: Load/Store Scheduling with No Store Queue at All

NoSQ: Store-Load Communication without a Store Queue

DMDC: Delayed Memory Dependence Checking through Age-Based Filtering

Coherence Ordering for Ring-based Chip Multiprocessors

In-Network Cache Coherence

ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers

An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget

Live, Runtime Phase Monitoring and Prediction on Real Systems with Application to Dynamic Power Management

Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units

Adaptive Caches: Effective Shaping of Cache Behavior to Workloads

Memory Prefetching Using Adaptive Stream Detection

Scalable Cache Miss Handling for High Memory-Level Parallelism

Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches

Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions

ASR: Adaptive Selective Replication for CMP Caches

Managing Distributed, Shared L2 Caches through OS-Level Page Allocation

Die Stacking (3D) Microarchitecture

Distributed Microarchitectural Protocols in the TRIPS Prototype Processor

Leveraging Optical Technology in Future Bus-based Chip Multiprocessors

Mitigating the Impact of Process Variations on Processor Register Files and Execution Units

Author Index

Yield-Aware Cache Architectures

Content Provider	ACM Digital Library
Author	Zhou, Hai Sinha, Debjit Ozdemir, Serkan Memik, Gokhan Adams, Jonathan
Abstract	One of the major issues faced by the semiconductor industry today is that of reducing chip yields. As the process technologies have scaled to smaller feature sizes, chip yields have dropped to around 50% or less. This figure is expected to decrease even further in future technologies. To attack this growing problem, we develop four yield-aware microarchitecture schemes for data caches. The first one is called Yield-Aware Power-Down (YAPD). YAPD turns off cache ways that cause delay violation and/or have excessive leakage. We also modify this approach to achieve better yields. This new method is called Horizontal YAPD (HYAPD), which turns off horizontal regions of the cache instead of ways. A third approach targets delay violation in data caches. Particularly, we develop a VAriable-latency Cache Architecture (VACA). VACA allows different load accesses to be completed with varying latencies. This is enabled by augmenting the functional units with special buffers that allow the dependants of a load operation to stall for a cycle if the load operation is delayed. As a result, if some accesses take longer than the predefined number of cycles, the execution can still be performed correctly, albeit with some performance degradation. A fourth scheme we devise is called the Hybrid mechanism, which combines the YAPD and the VACA. As a result of these schemes, chips that may be tossed away due to parametric yield loss can be saved. Experimental results demonstrate that the yield losses can be reduced by 68.1% and 72.4% with YAPD and HYAPD schemes and by 33.3% and 81.1% with VACA and Hybrid mechanisms, respectively, improving the overall yield to as much as 97.0%.
Starting Page	15
Ending Page	25
Page Count	11
File Format	PDF
ISBN	0769527329
ISSN	10724451
DOI	10.1109/MICRO.2006.52
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-12-09
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Yield-Aware Cache Architectures

Power-aware partitioned cache architectures

CATS: cache aware task-stealing based on online profiling in multi-socket multi-core architectures

ZerehCache: armoring cache architectures in high defect density technologies

Bank-aware dynamic cache partitioning for multicore architectures (2009)

Heterogeneity Aware Shared DRAM Cache for Integrated Heterogeneous Architectures

An active data-aware cache consistency protocol for highly-scalable data-shipping DBMS architectures

Bank-aware Dynamic Cache Partitioning for Multicore Architectures (2009)

LAWS: locality-aware work-stealing for multi-socket multi-core architectures

Yield-Aware Cache Architectures

Similar Documents

Yield-Aware Cache Architectures

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CATS: cache aware task-stealing based on online profiling in multi-socket multi-core architectures

ZerehCache: armoring cache architectures in high defect density technologies

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Yield-Aware Cache Architectures