NDLI: A Predictive Performance Model for Superscalar Processors

Please wait, while we are loading the content...

Message from the General Co-Chairs

Message from the Program Co-Chairs

Conference Committees

Reviewers

Sponsors

A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design

Yield-Aware Cache Architectures

Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware

PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection

Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths

Merging Head and Tail Duplication for Convergent Hyperblock Formation

Data-Dependency Graph Transformations for Superblock Scheduling

Dataflow Predication

Authentication Control Point and Its Implications For Secure Processor Design

Using Branch Correlation to Identify Infeasible Paths for Anomaly Detection

Memory Protection through Dynamic Access Control

LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting Security Attacks

Fairness and Throughput in Switch on Event Multithreading

A Predictive Performance Model for Superscalar Processors

Serialization-Aware Mini-Graphs: Performance with Fewer Resources

Architectural Support for Software Transactional Memory

Virtually Pipelined Network Memory

Fair Queuing Memory Systems

Reunion: Complexity-Effective Multicore Redundancy

Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers

CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs

Support for High-Frequency Streaming in CMPs

Fire-and-Forget: Load/Store Scheduling with No Store Queue at All

NoSQ: Store-Load Communication without a Store Queue

DMDC: Delayed Memory Dependence Checking through Age-Based Filtering

Coherence Ordering for Ring-based Chip Multiprocessors

In-Network Cache Coherence

ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers

An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget

Live, Runtime Phase Monitoring and Prediction on Real Systems with Application to Dynamic Power Management

Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units

Adaptive Caches: Effective Shaping of Cache Behavior to Workloads

Memory Prefetching Using Adaptive Stream Detection

Scalable Cache Miss Handling for High Memory-Level Parallelism

Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches

Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions

ASR: Adaptive Selective Replication for CMP Caches

Managing Distributed, Shared L2 Caches through OS-Level Page Allocation

Die Stacking (3D) Microarchitecture

Distributed Microarchitectural Protocols in the TRIPS Prototype Processor

Leveraging Optical Technology in Future Bus-based Chip Multiprocessors

Mitigating the Impact of Process Variations on Processor Register Files and Execution Units

Author Index

A Predictive Performance Model for Superscalar Processors

Content Provider	ACM Digital Library
Author	Vaswani, Kapil Joseph, P. J. Thazhuthaveetil, Matthew J.
Abstract	Designing and optimizing high performance microprocessors is an increasingly difficult task due to the size and complexity of the processor design space, high cost of detailed simulation and several constraints that a processor design must satisfy. In this paper, we propose the use of empirical non-linear modeling techniques to assist processor architects in making design decisions and resolving complex trade-offs. We propose a procedure for building accurate non-linear models that consists of the following steps: (i) selection of a small set of representative design points spread across processor design space using latin hypercube sampling, (ii) obtaining performance measures at the selected design points using detailed simulation, (iii) building non-linear models for performance using the function approximation capabilities of radial basis function networks, and (iv) validating the models using an independently and randomly generated set of design points. We evaluate our model building procedure by constructing non-linear performance models for programs from the SPEC CPU2000 benchmark suite with a microarchitectural design space that consists of 9 key parameters. Our results show that the models, built using a relatively small number of simulations, achieve high prediction accuracy (only 2.8% error in CPI estimates on average) across a large processor design space. Our models can potentially replace detailed simulation for common tasks such as the analysis of key microarchitectural trends or searches for optimal processor design points.
Starting Page	161
Ending Page	170
Page Count	10
File Format	PDF
ISBN	0769527329
ISSN	10724451
DOI	10.1109/MICRO.2006.6
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2006-12-09
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Predictive Performance Model for Superscalar Processors

A mechanistic performance model for superscalar in-order processors

Implementation of different branch prediction schemes on FabScalar generated superscalar processor

A Predictive Perfomance Model For Superscalar Processors

Performance Analysis of Superscalar Processors Using A Queueing Model (1997)

A time-stamping algorithm for efficient performance estimation of superscalar processors

Superscalar Processor Models Using Statistical Learning

A model to exploit power-performance efficiency in superscalar processors via structure resizing

Automated design of application specific superscalar processors: an analytical approach

A Predictive Performance Model for Superscalar Processors

Similar Documents

A Predictive Performance Model for Superscalar Processors

A mechanistic performance model for superscalar in-order processors

Implementation of different branch prediction schemes on FabScalar generated superscalar processor

A Predictive Perfomance Model For Superscalar Processors

Performance Analysis of Superscalar Processors Using A Queueing Model (1997)

A time-stamping algorithm for efficient performance estimation of superscalar processors

Superscalar Processor Models Using Statistical Learning

A model to exploit power-performance efficiency in superscalar processors via structure resizing

Automated design of application specific superscalar processors: an analytical approach

A Predictive Performance Model for Superscalar Processors