NDLI: Redefining the role of FPGAs in the next generation avionic systems (abstract only)

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Fast and effective placement and routing directed high-level synthesis for FPGAs

Modular multi-ported SRAM-based memories

Dynamic voltage & frequency scaling with online slack measurement

FPGA-based biophysically-meaningful modeling of olivocerebellar neurons

Soft vector processors with streaming pipelines

Hardware acceleration of database operations

Wordwidth, instructions, looping, and virtualization: the role of sharing in absolute energy minimization

Combining computation and communication optimizations in system synthesis for streaming applications

FPGA LUT design for wide-band dynamic voltage and frequency scaled operation (abstract only)

Transformations for throughput optimization in high-level synthesis (abstract only)

Future inter-FPGA communication architecture for multi-FPGA based prototyping (abstract only)

EPEE: an efficient PCIe communication library with easy-host-integration property for FPGA accelerators (abstract only)

Optimizing effective interconnect capacitance for FPGA power reduction

Revisiting and-inverter cones

Cad and routing architecture for interposer-based multi-FPGA systems

Square-rich fixed point polynomial evaluation on FPGAs

MORP: makespan optimization for processors with an embedded reconfigurable fabric

A scalable sparse matrix-vector multiplication kernel for energy-efficient sparse-blas on FPGAs

Theory and algorithm for generalized memory partitioning in high-level synthesis

Quantifying the cost and benefit of latency insensitive communication on FPGAs

A configurable mapreduce accelerator for multi-core FPGAs (abstract only)

On hybrid memory allocation for FPGA behavioral synthesis (abstract only)

1K manycore FPGA shared memory architecture for SOC (abstract only)

Implementing FPGA-based energy-efficient dense optical flow computation with high portability in C (abstract only)

Towards interconnect-adaptive packing for FPGAs

Scalable multi-access flash store for big data analytics

Memory block based scan-BIST architecture for application-dependent FPGA testing

Accelerating frequent item counting with FPGA

OmpSs@Zynq all-programmable SoC ecosystem

Binary stochastic implementation of digital logic

Using high-level synthesis and formal analysis to predict and preempt attacks on industrial control systems

MPack: global memory optimization for stream applications in high-level synthesis

A new basic logic structure for data-path computation (abstract only)

Pushing the performance boundary of linear projection designs through device specific optimisations (abstract only)

Non-adaptive sparse recovery and fault evasion using disjunct design configurations (abstract only)

Methodology to generate multi-dimensional systolic arrays for FPGAs using openCL (abstract only)

Rent's rule based FPGA packing for routability optimization

A power side-channel-based digital to analog converterfor Xilinx FPGAs

A FPGA prototype design emphasis on low power technique

Accelerating parameter estimation for multivariate self-exciting point processes

A soft error vulnerability analysis framework for Xilinx FPGAs

A methodology for identifying and placing heterogeneous cluster groups based on placement proximity data (abstract only)

Accelerating massive short reads mapping for next generation sequencing (abstract only)

Novel FPGA clock network with low latency and skew (abstract only)

Improving the security and the scalability of the AES algorithm (abstract only)

Energy-efficient multiplier-less discrete convolver through probabilistic domain transformation

A scalable routability-driven analytical placer with global router integration for FPGAs (abstract only)

Application specific processor with high level synthesized instructions (abstract only)

Asynchronous physical unclonable function using FPGA-based self-timed ring oscillator (abstract only)

Power estimation tool for system on programmable chip based platforms (abstract only)

Towards high performance GHASH for pipelined AES-GCM using FPGAs (abstract only)

Optimally mitigating BTI-induced FPGA device aging with discriminative voltage scaling (abstract only)

APMC: advanced pattern based memory controller (abstract only)

Using DSP blocks to compute CRC hash in FPGA (abstract only)

Hierarchical library-based power estimator for versatile FPGAs (abstract only)

Design, implementation and security analysis of hardware trojan threats in FPGA (abstract only)

On energy efficiency and amdahl's law in FPGA based chip heterogeneous multiprocessor systems (abstract only)

An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only)

A power-efficient adaptive heapsort for fpga-based image coding application (abstract only)

Producing high-quality real-time HDR video system with FPGA (abstract only)

Exploring duty cycle distortions along signal paths in FPGAs (abstract only)

Big data genome sequencing on Zynq based clusters (abstract only)

xDEFENSE: an extended DEFENSE for mitigating next generation intrusions (abstract only)

BMP: a fast B*-tree based modular placer for FPGAs (abstract only)

Coordinating routing resources for hex pips test in island-style FPGAs (abstract only)

Redefining the role of FPGAs in the next generation avionic systems (abstract only)

Pipelining FPPGA-based defect detction in FPDs (abstract only)

Co-processing with dynamic reconfiguration on heterogeneous MPSoC: practices and design tradeoffs (abstract only)

Control signal aware slice-level window based legalization method for FPGA placement (abstract only)

Redefining the role of FPGAs in the next generation avionic systems (abstract only)

Content Provider	ACM Digital Library
Author	Viswanathan, Venkatasubramanian Nakache, Benjamin Ben Atitallah, Rabie Nakache, Maurice Dekeyser, Jean-Luc
Abstract	Embedded reconfigurable computing is becoming a new paradigm for system designers in avionic applications. In fact, FPGAs can be used for more than just computational purpose in order to improve the system performance. The introduction of FPGA Mezzanine Card (FMC) I/O standard has given a new purpose for FPGAs to be used as a communication platform. Taking into account the features offered by FPGAs and FMCs, such as runtime reconfiguration and modularity, we have redefined the role of these devices to be used as a generic communication and computation-centric platform. A new modular, runtime reconfigurable, Intellectual Property (IP)-based communication-centric platform for avionic applications has been designed. This means that, when the communication requirement of an avionic system changes, the necessary communication protocol is installed and executed on demand, without disturbing the normal operation of a time-critical avionic system. The efficiency and the performances of our platform are illustrated through a real industrial use-case designed using a computationally intensive application and several avionic I/O bus standards. The reconfiguration latency can be hidden totally in many cases. While in certain others, the overhead of reconfiguration can be justified by the reduction in the resource utilization.
Starting Page	248
Ending Page	248
Page Count	1
ISBN	9781450326711
DOI	10.1145/2554688.2554744
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-02-26
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Intensive signal processing applications Fpga mezzanine module Dynamic partial reconfiguration Avionic ip cores Modular and reconfigurable i/os
Content Type	Text
Resource Type	Article

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