NDLI: Revisiting and-inverter cones

Please wait, while we are loading the content...

Fast and effective placement and routing directed high-level synthesis for FPGAs

Modular multi-ported SRAM-based memories

Dynamic voltage & frequency scaling with online slack measurement

FPGA-based biophysically-meaningful modeling of olivocerebellar neurons

Soft vector processors with streaming pipelines

Hardware acceleration of database operations

Wordwidth, instructions, looping, and virtualization: the role of sharing in absolute energy minimization

Combining computation and communication optimizations in system synthesis for streaming applications

FPGA LUT design for wide-band dynamic voltage and frequency scaled operation (abstract only)

Transformations for throughput optimization in high-level synthesis (abstract only)

Future inter-FPGA communication architecture for multi-FPGA based prototyping (abstract only)

EPEE: an efficient PCIe communication library with easy-host-integration property for FPGA accelerators (abstract only)

Optimizing effective interconnect capacitance for FPGA power reduction

Revisiting and-inverter cones

Cad and routing architecture for interposer-based multi-FPGA systems

Square-rich fixed point polynomial evaluation on FPGAs

MORP: makespan optimization for processors with an embedded reconfigurable fabric

A scalable sparse matrix-vector multiplication kernel for energy-efficient sparse-blas on FPGAs

Theory and algorithm for generalized memory partitioning in high-level synthesis

Quantifying the cost and benefit of latency insensitive communication on FPGAs

A configurable mapreduce accelerator for multi-core FPGAs (abstract only)

On hybrid memory allocation for FPGA behavioral synthesis (abstract only)

1K manycore FPGA shared memory architecture for SOC (abstract only)

Implementing FPGA-based energy-efficient dense optical flow computation with high portability in C (abstract only)

Towards interconnect-adaptive packing for FPGAs

Scalable multi-access flash store for big data analytics

Memory block based scan-BIST architecture for application-dependent FPGA testing

Accelerating frequent item counting with FPGA

OmpSs@Zynq all-programmable SoC ecosystem

Binary stochastic implementation of digital logic

Using high-level synthesis and formal analysis to predict and preempt attacks on industrial control systems

MPack: global memory optimization for stream applications in high-level synthesis

A new basic logic structure for data-path computation (abstract only)

Pushing the performance boundary of linear projection designs through device specific optimisations (abstract only)

Non-adaptive sparse recovery and fault evasion using disjunct design configurations (abstract only)

Methodology to generate multi-dimensional systolic arrays for FPGAs using openCL (abstract only)

Rent's rule based FPGA packing for routability optimization

A power side-channel-based digital to analog converterfor Xilinx FPGAs

A FPGA prototype design emphasis on low power technique

Accelerating parameter estimation for multivariate self-exciting point processes

A soft error vulnerability analysis framework for Xilinx FPGAs

A methodology for identifying and placing heterogeneous cluster groups based on placement proximity data (abstract only)

Accelerating massive short reads mapping for next generation sequencing (abstract only)

Novel FPGA clock network with low latency and skew (abstract only)

Improving the security and the scalability of the AES algorithm (abstract only)

Energy-efficient multiplier-less discrete convolver through probabilistic domain transformation

A scalable routability-driven analytical placer with global router integration for FPGAs (abstract only)

Application specific processor with high level synthesized instructions (abstract only)

Asynchronous physical unclonable function using FPGA-based self-timed ring oscillator (abstract only)

Power estimation tool for system on programmable chip based platforms (abstract only)

Towards high performance GHASH for pipelined AES-GCM using FPGAs (abstract only)

Optimally mitigating BTI-induced FPGA device aging with discriminative voltage scaling (abstract only)

APMC: advanced pattern based memory controller (abstract only)

Using DSP blocks to compute CRC hash in FPGA (abstract only)

Hierarchical library-based power estimator for versatile FPGAs (abstract only)

Design, implementation and security analysis of hardware trojan threats in FPGA (abstract only)

On energy efficiency and amdahl's law in FPGA based chip heterogeneous multiprocessor systems (abstract only)

An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only)

A power-efficient adaptive heapsort for fpga-based image coding application (abstract only)

Producing high-quality real-time HDR video system with FPGA (abstract only)

Exploring duty cycle distortions along signal paths in FPGAs (abstract only)

Big data genome sequencing on Zynq based clusters (abstract only)

xDEFENSE: an extended DEFENSE for mitigating next generation intrusions (abstract only)

BMP: a fast B*-tree based modular placer for FPGAs (abstract only)

Coordinating routing resources for hex pips test in island-style FPGAs (abstract only)

Redefining the role of FPGAs in the next generation avionic systems (abstract only)

Pipelining FPPGA-based defect detction in FPDs (abstract only)

Co-processing with dynamic reconfiguration on heterogeneous MPSoC: practices and design tradeoffs (abstract only)

Control signal aware slice-level window based legalization method for FPGA placement (abstract only)

Revisiting and-inverter cones

Content Provider	ACM Digital Library
Author	Yang, Liqun Yang, Haigang Zgheib, Grace Huang, Zhihong Novo, David Ienne, Paolo Parandeh-Afshar, Hadi
Abstract	And-Invert Cones (AICs) have been suggested as an alternative to the ubiquitous Look-Up Tables (LUTs) used in commercial FPGAs. The original article suggesting the new architecture made some untested assumptions on the circuitry needed to implement AIC architectures and did not develop completely the toolset necessary to assess comprehensively the idea. In this paper, we pick up the architecture that some of us proposed in the original AIC paper and try to implement it as thoroughly as we can afford. We build all components for the logic cluster at transistor level in a 40~nm technology as well as a LUT-based architecture inspired by Altera's Stratix~IV. We first determine that the characteristics of our LUT-based architecture are reasonably similar to those of the commercial counterpart. Then, we compare the AIC architecture to the baseline on a number of benchmarks, and we find a few difficulties that had been overlooked before. We thus explore other design possibilities around the original design point and show their detailed impact. Finally, we discuss how the very structure of current logic clusters seems not perfectly appropriate for getting the best out of AICs and conclude that, even though they are not confirmed as an immediate blessing today, AICs still offer rich research opportunities.
Starting Page	45
Ending Page	54
Page Count	10
File Format	PDF
ISBN	9781450326711
DOI	10.1145/2554688.2554791
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-02-26
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	And-inverter cones Fpga logic block Transistor design Fpga architecture
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in