NDLI: A FPGA prototype design emphasis on low power technique

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A FPGA prototype design emphasis on low power technique

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A FPGA prototype design emphasis on low power technique

Content Provider	ACM Digital Library
Author	Hanyang, Xu Meilai, Jin Jian, Wang
Abstract	In this paper, we propose a fully-functional Nanometer FPGA prototype chip. Compared to traditional single supply voltage, single threshold voltage design, we explore low power nanometer FPGA design challenges with Multi-Vt, Static Voltage Scaling and sleep mode technique. Compared to Dynamic Voltage Scaling (DVS), we make a table of Voltage-Delay parameter pairs under different voltage conditions so that timing information can be calculated by a Static Timing Analysis (STA) tool. Thus a lowest supply power is chosen among all results which meet the timing requirements. This approach would simplify the hardware design since we don't need a complex workload detection circuit compared to DVS system. By separating supply voltages, we can directly shutdown power supply of the unused circuits. Compared to inserting sleep transistor in pull-up or pull-down networks, we can eliminate the speed penalty cased by the additional sleep transistor. We implement a tile-based heterogeneous architecture with island style routing and embedded specific blocks such as DSP and memory. The array size is 64×31 (Row×Col) including 64×24 CLBs. The final design is fabricated using a 1P10M 65-nm bulk CMOS process. Test results show a 53% reduction in static power compared to a commercial FPGA device which is also fabricated in 65nm process and has a similar array size.
Starting Page	147
Ending Page	150
Page Count	4
File Format	PDF
ISBN	9781450326711
DOI	10.1145/2554688.2554762
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-02-26
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Leakage Multi-vt Voltage scaling Dynamic Sleep mode Fpga Lut Multiple supply voltage
Content Type	Text
Resource Type	Article

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