NDLI: Modular multi-ported SRAM-based memories

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Fast and effective placement and routing directed high-level synthesis for FPGAs

Modular multi-ported SRAM-based memories

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Modular multi-ported SRAM-based memories

Content Provider	ACM Digital Library
Author	Abdelhadi, Ameer M.S. Lemieux, Guy G.F.
Abstract	Multi-ported RAMs are essential for high-performance parallel computation systems. VLIW and vector processors, CGRAs, DSPs, CMPs and other processing systems often rely upon multi-ported memories for parallel access, hence higher performance. Although memories with a large number of read and write ports are important, their high implementation cost means they are used sparingly in designs. As a result, FPGA vendors only provide dual-ported block RAMs to handle the majority of usage patterns. In this paper, a novel and modular approach is proposed to construct multi-ported memories out of basic dual-ported RAM blocks. Like other multi-ported RAM designs, each write port uses a different RAM bank and each read port uses bank replication. The main contribution of this work is an optimization that merges the previous live-value-table (LVT) and XOR approaches into a common design that uses a generalized, simpler structure we call an invalidation-based live-value-table (I-LVT). Like a regular LVT, the I-LVT determines the correct bank to read from, but it differs in how updates to the table are made; the LVT approach requires multiple write ports, often leading to an area-intensive register-based implementation, while the XOR approach uses wider memories to accommodate the XOR-ed data and suffers from lower clock speeds. Two specific I-LVT implementations are proposed and evaluated, binary and one-hot coding. The I-LVT approach is especially suitable for larger multi-ported RAMs because the table is implemented only in SRAM cells. The I-LVT method gives higher performance while occupying less block RAMs than earlier approaches: for several configurations, the suggested method reduces the block RAM usage by over 44% and improves clock speed by over 76%. To assist others, we are releasing our fully parameterized Verilog implementation as an open source hardware library. The library has been extensively tested using ModelSim and Altera's Quartus tools.
Starting Page	35
Ending Page	44
Page Count	10
File Format	PDF
ISBN	9781450326711
DOI	10.1145/2554688.2554773
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	2014-02-26
Publisher Place	New York
Access Restriction	Subscribed
Subject Keyword	Parallel memory access Embedded memory Programmable memory Cache memory Register-file Block ram multi-ported memory Shared memory
Content Type	Text
Resource Type	Article

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