NDLI: A large, fast instruction window for tolerating cache misses

Content Provider	ACM Digital Library
Author	Lebeck, Alvin R. Patwardhan, Jaidev Koppanalil, Jinson Li, Tong Rotenberg, Eric
Abstract	Instruction window size is an important design parameter for many modern processors. Large instruction windows offer the potential advantage of exposing large amounts of instruction level parallelism. Unfortunately naively scaling conventional window designs can significantly degrade clock cycle time, undermining the benefits of increased parallelism.This paper presents a new instruction window design targeted at achieving the latency tolerance of large windows with the clock cycle time of small windows. The key observation is that instructions dependent on a long latency operation (e.g., cache miss) cannot execute until that source operation completes. These instructions are moved out of the conventional, small, issue queue to a much larger waiting instruction buffer (WIB). When the long latency operation completes, the instructions are reinserted into the issue queue. In this paper, we focus specifically on load cache misses and their dependent instructions. Simulations reveal that, for an 8-way processor, a 2K-entry WIB with a 32-entry issue queue can achieve speedups of 20%, 84%, and 50% over a conventional 32-entry issue queue for a subset of the SPEC CINT2000, SPEC CFP2000, and Olden benchmarks, respectively.
Starting Page	59
Ending Page	70
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/545214.545223
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	30
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Instruction window memory latency cache memory latency tolerance
Content Type	Text
Resource Type	Article

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