NDLI: Managing multi-configuration hardware via dynamic working set analysis

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Volume 30, Issue 5, December 2002

Volume 30, Issue 4, September 2002

Volume 30, Issue 3, June 2002

Volume 30, Issue 2, May 2002

The optimum pipeline depth for a microprocessor

Efficient dynamic scheduling through tag elimination

Transient-fault recovery using simultaneous multithreading

Dynamic fine-grain leakage reduction using leakage-biased bitlines

Using a user-level memory thread for correlation prefetching

Timekeeping in the memory system

Speculative dynamic vectorization

Design tradeoffs for the Alpha EV8 conditional branch predictor

The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays

Detailed design and evaluation of redundant multithreading alternatives

Avoiding initialization misses to the heap

Implementing optimizations at decode time

Experiences with VI communication for database storage

Difficult-path branch prediction using subordinate microthreads

Increasing processor performance by implementing deeper pipelines

A large, fast instruction window for tolerating cache misses

Power and performance evaluation of globally asynchronous locally synchronous processors

Going the distance for TLB prefetching

Managing multi-configuration hardware via dynamic working set analysis

A scalable instruction queue design using dependence chains

An instruction set and microarchitecture for instruction level distributed processing

Volume 30, Issue 1, March 2002

Managing multi-configuration hardware via dynamic working set analysis

Content Provider	ACM Digital Library
Author	Smith, James E. Dhodapkar, Ashutosh S.
Abstract	Microprocessors are designed to provide good average performance over a variety of workloads. This can lead to inefficiencies both in power and performance for individual programs and during individual phases within the same program. Microarchitectures with multi-configuration units (e.g. caches, predictors, instruction windows) are able to adapt dynamically to program behavior and enable/disable resources as needed. A key element of existing configuration algorithms is adjusting to program phase changes. This is typically done by "tuning" when a phase change is detected --- i.e. sequencing through a series of trial configurations and selecting the best.Algorithms that dynamically collect and analyze program working set information are studied. To make this practical, we propose working set signatures --- highly compressed working set representations (e.g. 32-128 bytes total). Algorithms use working set signatures to 1) detect working set changes and trigger re-tuning; 2) identify, recurring working sets and re-install saved optimal reconfigurations, thus avoiding the time-consuming tuning process; 3) estimate working set sizes to configure caches directly to the proper size, also avoiding the tuning process. Multi-configuration instruction caches are used to demonstrate the performance of the proposed algorithms. When applied to reconfigurable instruction caches, an algorithm that identifies recurring phases achieves power savings and performance similar to the best algorithm reported to date, but with orders-of-magnitude savings in the number of re-tunings.
Starting Page	233
Ending Page	244
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/545214.545241
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	30
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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