NDLI: The optimum pipeline depth for a microprocessor

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Volume 30, Issue 5, December 2002

Volume 30, Issue 4, September 2002

Volume 30, Issue 3, June 2002

Volume 30, Issue 2, May 2002

The optimum pipeline depth for a microprocessor

Efficient dynamic scheduling through tag elimination

Transient-fault recovery using simultaneous multithreading

Dynamic fine-grain leakage reduction using leakage-biased bitlines

Using a user-level memory thread for correlation prefetching

Timekeeping in the memory system

Speculative dynamic vectorization

Design tradeoffs for the Alpha EV8 conditional branch predictor

The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays

Detailed design and evaluation of redundant multithreading alternatives

Avoiding initialization misses to the heap

Implementing optimizations at decode time

Experiences with VI communication for database storage

Difficult-path branch prediction using subordinate microthreads

Increasing processor performance by implementing deeper pipelines

A large, fast instruction window for tolerating cache misses

Power and performance evaluation of globally asynchronous locally synchronous processors

Going the distance for TLB prefetching

Managing multi-configuration hardware via dynamic working set analysis

A scalable instruction queue design using dependence chains

An instruction set and microarchitecture for instruction level distributed processing

Volume 30, Issue 1, March 2002

The optimum pipeline depth for a microprocessor

Content Provider	ACM Digital Library
Author	Puzak, Thomas R. Hartstein, A.
Abstract	The impact of pipeline length on the performance of a microprocessor is explored both theoretically and by simulation. An analytical theory is presented that shows two opposing architectural parameters affect the optimal pipeline length: the degree of instruction level parallelism (superscalar) decreases the optimal pipeline length, while the lack of pipeline stalls increases the optimal pipeline length. This theory is tested by analyzing the optimal pipeline length for 35 applications representing three classes of workloads. Trace tapes are collected from SPEC95 and SPEC2000 applications, traditional (legacy) database and on-line transaction processing (OLTP) applications, and modern (e. g. web) applications primarily written in Java and C++. The results show that there is a clear and significant difference in the optimal pipeline length between the SPEC workloads and both the legacy and modern applications. The SPEC applications, written in C, optimize to a shorter pipeline length than the legacy applications, largely written in assembler language, with relatively little overlap in the two distributions. Additionally, the optimal pipeline length distribution for the C++ and Java workloads overlaps with the legacy applications, suggesting similar workload characteristics. These results are explored across a wide range of superscalar processors, both in-order and out-of-order.
Starting Page	7
Ending Page	13
Page Count	7
File Format	PDF
ISSN	01635964
DOI	10.1145/545214.545217
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	30
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Content Type	Text
Resource Type	Article

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