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A Large, Fast Instruction Window for Tolerating Cache Misses (2002)
| Content Provider | CiteSeerX |
|---|---|
| Author | Patwardhan, Jaidev Li, Tong Lebeck, Alvin R. Koppanalil, Jinson Rotenberg, Eric |
| Description | In International Symposium on Computer Architecture |
| Abstract | Instruction window size is an important design parameter for many modern processors. Large instruction windows offer the potential advantage of exposing large amounts of instruction level parallelism. Unfortunately, naively scaling conventional window designs can significantly degrade clock cycle time, undermining the benefits of increased parallelism. This paper presents a new instruction window design targeted at achieving the latency tolerance of large windows with the clock cycle time of small windows. The key observation is that instructions dependent on a long latency operation (e.g., cache miss) cannot execute until that source operation completes. These instructions are moved out of the conventional, small, issue queue to a much larger waiting instruction buffer (WIB). When the long latency operation completes, the instructions are reinserted into the issue queue. In this paper, we focus specifically on load cache misses and their dependent instructions. Simulations reveal that, for an 8-way processor, a 2K-entry WIB with a 32entry issue queue can achieve speedups of 20%, 84%, and 50% over a conventional 32-entry issue queue for a subset of the SPEC CINT2000, SPEC CFP2000, and Olden benchmarks, respectively. |
| File Format | |
| Publisher Date | 2002-01-01 |
| Access Restriction | Open |
| Subject Keyword | Latency Tolerance Spec Cint2000 Many Modern Processor Cannot Execute Large Window Load Cache Miss 8-way Processor Spec Cfp2000 Instruction Buffer Small Window Long Latency Operation Clock Cycle Time Instruction Window Size Increased Parallelism New Instruction Window Design Cache Miss Conventional 32-entry Issue Queue Large Instruction Window Long Latency Operation Completes Important Design Parameter Conventional Window Design 2k-entry Wib Potential Advantage Olden Benchmark Source Operation Completes Issue Queue Dependent Instruction Key Observation Instruction Level Parallelism Fast Instruction Window |
| Content Type | Text |
| Resource Type | Conference Proceedings Article |
