NDLI: Using a user-level memory thread for correlation prefetching

Content Provider	ACM Digital Library
Author	Torrellas, Josep Solihin, Yan Lee, Jaejin
Abstract	This paper introduces the idea of using a User-Level Memory Thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main memory, either in the memory controller chip or in a DRAM chip. The thread performs correlation prefetching in software, sending the prefetched data into the L2 cache of the main processor. This approach requires minimal hardware beyond the memory processor: the correlation table is a software data structure that resides in main memory, while the main processor only needs a few modifications to its L2 cache so that it can accept incoming prefetches. In addition, the approach has wide usability, as it can effectively prefetch even for irregular applications. Finally, it is very flexible, as the prefetching algorithm can be customized by the user on an application basis. Our simulation results show that, through a new design of the correlation table and prefetching algorithm, our scheme delivers good results. Specifically, nine mostly-irregular applications show an average speedup of 1.32. Furthermore, our scheme works well in combination with a conventional processor-side sequential prefetcher, in which case the average speedup increases to 1.46. Finally, by exploiting the customization of the prefetching algorithm, we increase the average speedup to 1.53.
Starting Page	171
Ending Page	182
Page Count	12
File Format	PDF
ISSN	01635964
DOI	10.1145/545214.545235
Journal	ACM SIGARCH Computer Architecture News (CARN)
Volume Number	30
Issue Number	2
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1981-04-01
Publisher Place	New York
Access Restriction	One Nation One Subscription (ONOS)
Subject Keyword	Data prefetching intelligent memory processing-in-memory computer architecture correlation prefetching memory hierarchies caches threads
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Using a user-level memory thread for correlation prefetching

Prefetching in an Intelligent Memory Architecture Using a Helper Thread

Prefetching in an intelligent memory architecture using a helper thread.

Correlation prefetching with a user-level memory thread

Prefetching in an intelligent memory architecture using a helper.

Sequential Program Prefetching in Memory Hierarchies

Using a user-level memory thread for correlation prefetching

Using a User-Level Memory Thread for Correlation Prefetching (2002)

Using a User-Level Memory Thread for Correlation Prefetching (2002)

Using a user-level memory thread for correlation prefetching

Similar Documents

Using a user-level memory thread for correlation prefetching

Prefetching in an Intelligent Memory Architecture Using a Helper Thread

Prefetching in an intelligent memory architecture using a helper thread.

Correlation prefetching with a user-level memory thread

Prefetching in an intelligent memory architecture using a helper.

Sequential Program Prefetching in Memory Hierarchies

Using a user-level memory thread for correlation prefetching

Using a User-Level Memory Thread for Correlation Prefetching (2002)

Using a User-Level Memory Thread for Correlation Prefetching (2002)

Using a user-level memory thread for correlation prefetching