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| Content Provider | ACM Digital Library |
|---|---|
| Author | Sivasubramaniam, Anand Kandiraju, Gokul B. |
| Abstract | The importance of the Translation Lookaside Buffer (TLB) on system performance is well known. There have been numerous prior efforts addressing TLB design issues for cutting down access times and lowering miss rates. However, it was only recently that the first exploration [26] on prefetching TLB entries ahead of their need was undertaken and a mechanism called Recency Prefetching was proposed. There is a large body of literature on prefetching for caches, and it is not clear how they can be adapted (or if the issues are different) for TLBs, how well suited they are for TLB prefetching, and how they compare with the recency prefetching mechanism.This paper presents the first detailed comparison of different prefetching mechanisms (previously proposed for caches) - arbitrary stride prefetching, and markov prefetching - for TLB entries, and evaluates their pros and cons. In addition, this paper proposes a novel prefetching mechanism, called Distance Prefetching, that attempts to capture patterns in the reference behavior in a smaller space than earlier proposals. Using detailed simulations of a wide variety of applications (56 in all) from different benchmark suites and all the SPEC CPU2000 applications, this paper demonstrates the benefits of distance prefetching. |
| Starting Page | 195 |
| Ending Page | 206 |
| Page Count | 12 |
| File Format | |
| ISSN | 01635964 |
| DOI | 10.1145/545214.545237 |
| Journal | ACM SIGARCH Computer Architecture News (CARN) |
| Volume Number | 30 |
| Issue Number | 2 |
| Language | English |
| Publisher | Association for Computing Machinery (ACM) |
| Publisher Date | 1981-04-01 |
| Publisher Place | New York |
| Access Restriction | One Nation One Subscription (ONOS) |
| Subject Keyword | Memory hierarchy Prefetching Simulation Application-driven study Translation lookaside buffer |
| Content Type | Text |
| Resource Type | Article |
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