NDLI: Phase-error cancellation technique for fast-lock phase-locked loop

Content Provider	IET Digital Library
Author	Ding, Zhaoming Liu, Haiqi Li, Qiang
Abstract	This paper presents a phase-error cancellation (PEC) technique that can be employed to achieve fast lock in analogue phase-locked loops (PLLs). The PLL works in fast-lock mode during phase and frequency tracking, and is switched to normal mode after it is almost locked. Unstable system topology is introduced in this system for fast locking. This PEC technique is proposed to cancel the phase error when the output frequency approaches the target value. Due to the inherent oscillation nature of the intentionally designed unstable system in fast-lock mode, the time for PEC can be predicted based on some known parameters. A PLL is simulated in 0.13 µm CMOS process with 1.2 V supply to verify the proposed PEC technique. Simulation results prove that this technique can reduce at least 87% settling time as compared with conventional PLLs.
Starting Page	417
Ending Page	422
Page Count	6
ISSN	1751858X
Volume Number	10
e-ISSN	17518598
Issue Number	Issue 5, Sep (2016)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/10/5
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2015.0201
Journal	IET Circuits, Devices & Systems
Publisher Date	2016-09-01
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Analogue Circuit Analogue Circuit Design Analogue Phase Locked Loop Circuit Stability CMOS Analogue Integrated Circuit CMOS Integrated Circuit CMOS Process Demodulator Discriminators And Mixers Fast Lock Phase Locked Loop Modelling Modulator Oscillation Nature Phase Error Cancellation Technique Phase Locked Loop Size 0.13 Mum Testing Voltage 1.2 V
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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