NDLI: Assessment of interface traps in In0.53Ga0.47As FinFET with gate-to-source/drain underlap for sub-14 nm technology node to impede short channel effect

Content Provider	IET Digital Library
Author	Pathak, Jay Darji, Anand
Abstract	Silicon fin field-effect transistor (FinFET) devices with gate–source/drain underlap fin length (L un) structures have been used for effective reduction in short channel effects (SCEs) from many years. Here, investigations have been performed on the FinFET structure with In0.53Ga0.47As material. Three-dimensional technology computer-aided design simulations for 14 nm channel length In0.53Ga0.47As FinFETs with underlap have been conducted by incorporating various effects to analyse the influence of interface traps on the device. The dominance of traps is investigated on SCE and intrinsic delay to assess the trend on underlap devices. The impact on threshold voltage and on current due to metal gate work function (MGWF) variation has been also demonstrated. Simulations have been carried out for L un = 0, 3, 6, and 9 nm with interface trap density of 1012 and 1014 cm–2 eV–1. Improvement in the subthreshold swing (SS) is observed as the L un increases but at the cost of intrinsic delay. However, the improvement in SS after L un = 6 nm is nearly constant. It has been also observed that the relative standard deviation of the threshold voltage and on current variation due to MGWF variation improves as the L un increases till 6 nm after that this improvement is not very significant.
Starting Page	428
Ending Page	434
Page Count	7
ISSN	1751858X
Volume Number	13
e-ISSN	17518598
Issue Number	Issue 4, Jul (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/13/4
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.5319
Journal	IET Circuits, Devices & Systems
Publisher Date	2018-10-24
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Design And Testing Elemental Semiconductor Equivalent Circuit FinFET Structure Gallium Arsenide Gate–source-drain Underlap Fin Length III-V SemiConductor In0.53Ga0.47As Indium Compound Insulated Gate Field Effect Transistors Interface Trap Density Metal Gate Work Function Variation MGWF Variation MOSFET Semiconductor Device Model Semiconductor Device Modelling Short Channel Effect Silicon Silicon Fin Field-effect Transistor Device Size 0.0 Nm Size 14.0 Nm Size 3.0 Nm Size 6.0 Nm Size 9.0 Nm Standard Deviation Subthreshold Swing Three-dimensional Technology Computer-aided Design Simulations Threshold Voltage Underlap Device Work Function
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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