NDLI: Timing error detection and correction for power efficiency: an aggressive scaling approach

Content Provider	IET Digital Library
Author	Rathnala, Prasanthi Wilmshurst, Tim Kharaz, Ahmad
Abstract	Low-power consumption has become an important aspect of processors and systems design. Many techniques ranging from architectural to system level are available. Voltage scaling or frequency boosting methods are the most effective to achieve low-power consumption as the dynamic power is proportional to the frequency and to the square of the supply voltage. The basic principle of operation of aggressive voltage scaling is to adjust the supply voltage to the lowest level possible to achieve minimum power consumption while maintaining reliable operations. Similarly, aggressive frequency boosting is to alter the operating frequency to achieve optimum performance improvement. In this study, an aggressive technique which employs voltage or frequency varying hardware circuit with the time-borrowing feature is presented. The proposed technique double samples the data to detect any timing violations as the frequency/voltage is scaled. The detected violations are masked by phase delaying the flip-flop clock to capture the late arrival data. This makes the system timing error tolerant without incurring error correction timing penalty. The proposed technique is implemented in a field programmable gate array using a two-stage arithmetic pipeline. Results on various benchmarks clearly demonstrate the achieved power savings and performance improvement.
Starting Page	707
Ending Page	712
Page Count	6
ISSN	1751858X
Volume Number	12
e-ISSN	17518598
Issue Number	Issue 6, Nov (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/12/6
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.5143
Journal	IET Circuits, Devices & Systems
Publisher Date	2018-09-11
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Aggressive Frequency Boosting Aggressive Scaling Approach Aggressive Voltage Scaling Clocks Dynamic Power Error Correction Error Correction Timing Penalty Error Detection Error Detection Timing Field Programmable Gate Array Flip Flops Flip-flop Frequency Varying Hardware Circuit Latch Combination Logic And Switching Circuit Logic Circuit Low Power Electronics Low-power Consumption Minimum Power Consumption Phase Delaying Power Consumption Power Efficiency Power Savings Processors Supervisory Control Signal System Design System Level System Timing Error Tolerant Time-borrowing Feature Timing Violation Detection Two-stage Arithmetic Pipeline
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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