NDLI: Low supply voltage and multiphase all-digital crystal-less clock generator

Content Provider	IET Digital Library
Author	Tu, Yo Hao Liu, Jen Chieh Cheng, Kuo Hsing Chang, Chi Yang
Abstract	A multiphase all-digital crystal-less clock generator (CLCG) with an interpolating digital controlled oscillator (DCO) that achieves an operating frequency of 500 MHz with 10-phase outputs is proposed. The CLCG adopts a specific temperature coefficient of a time-to-digital convertor (TDC) to create a positive or negative temperature coefficient and compensates for the DCO frequency drift. A time amplifier (TA) can extend the timing resolution of the TDC and reduce the effects of process variations in order to tune the TA gains. The frequency compensator adopts the frequency difference between the ring oscillator and DCO to reduce the frequency drift. The frequency accuracy is 69 ppm/°C from − 20 to 80°C. The root mean square jitter and output phase noise are 3.86 ps and − 100.36 dBc/Hz at 1 MHz, respectively. The core area of the test chip is 350 × 420 μm2 in a 65-nm CMOS process. At a supply voltage of 0.6 V, the power consumption is 1.8 mW for the 5 Gb/s clocking system.
Starting Page	720
Ending Page	725
Page Count	6
ISSN	1751858X
Volume Number	12
e-ISSN	17518598
Issue Number	Issue 6, Nov (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/12/6
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.5149
Journal	IET Circuits, Devices & Systems
Publisher Date	2018-08-29
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	10-phase Outputs A/D And D/A Convertor Bit Rate 5 Gbit/s CLCG Clocks CMOS Integrated Circuit CMOS Process DCO Frequency Drift Digital Circuit Digital Controlled Oscillator Electrical/electronic Equipment Energy Utilisation Frequency 1.0 MHz Frequency 500.0 MHz Frequency Compensator Interpolation And Function Approximation Jitter Low Power Electronics Low Supply Voltage Mean Square Error Method Multiphase All-digital Crystal-less Clock Generator Negative Temperature Coefficient Numerical Analysis Numerical Approximation And Analysis Oscillator Output Phase Noise Phase Noise Positive Temperature Coefficient Power 1.8 MW Ring Oscillator Root Mean Square Jitter Size 350 Mum Size 420 Mum Size 65 Nm TDC Temperature 20 DegC to 80 DegC Time 3.86 Ps Time Amplifier Time-digital Conversion Time-to-digital Converter Timing Resolution UHF Oscillator Voltage 0.6 V
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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