NDLI: Hetro8T: power and area efficient approximate heterogeneous 8T SRAM for H.264 video decoder

Content Provider	IET Digital Library
Author	Bharti, Pramod Kumar Surana, Neelam Mekie, Joycee
Abstract	Wide-spread availability of high-speed INTERNET and rapid increase of smart-phone users have significantly increased online video surfing. Video decoders like H.264/H.265/MPEG consume a significant amount of power in Static Random Access Memory (SRAM) buffers. In this study, the authors propose a 1 kb (32 × 32) heterogeneous 8T SRAM architectures with (2-lower order bits) and without truncation for H.264 video decoder. They have used heterogeneous sized SRAM design and bit-truncation techniques are used simultaneously to obtain low power memory design for the H.264 video decoder. They show that the proposed approximate memory used for H.264 video decoder provide high video quality even at low power and low area budget of 0.3 µW/pixel and 5.2 µm2/pixel, respectively, at 0.5 V and 20 MHz in UMC 28 nm CMOS technology. The proposed memory architecture is compared with existing approximate memories such as heterogeneous 6T, hybrid 8T/6T, all-identical 6T, and all-identical 8T SRAM memory. The results show that proposed memory architectures perform cumulatively better than existing techniques in terms of dynamic power, leakage power, and area.
Starting Page	505
Ending Page	513
Page Count	9
ISSN	17518601
Volume Number	13
e-ISSN	1751861X
Issue Number	Issue 6, Nov (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cdt/13/6
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2019.0019
Journal	IET Computers & Digital Techniques
Publisher Date	2019-06-19
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Approximate Memory Bit-truncation Technique CMOS Integrated Circuit Decoding Frequency 20.0 MHz H.264 Video Decoder H.265 Video Decoder Heterogeneous 8T SRAM Architectures Heterogeneous Sized SRAM Design Hetro8T High Video Quality High-speed Internet Image And Video Coding Integrated Circuit Design Layout Low Area Budget Low Power Electronics Low Power Memory Design Memory Architecture Memory Circuit Modelling And Testing MPEG Video Decoder Online Video Surfing Semiconductor Integrated Circuit Design Semiconductor Storage Size 28.0 Nm SRAM Chips Static Random Access Memory Buffers Storage Requirements UMC 28 Nm CMOS Technology Video Coding Video Signal Processing Voltage 0.5 V
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Software

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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