NDLI: Design optimisation procedure for digital mismatch compensation in latch comparators

Content Provider	IET Digital Library
Author	Khanfir, Leïla Mouïne, Jaouhar
Abstract	Digital calibration schemes generally allow for high-speed operation and reduced power consumption at the price of lower accuracy compared with their analogue counterparts. However, in dynamic comparators, when exceeding 4 or 5 bits, any resolution increase will be progressively traded against the circuit parameters. This study presents a three-step design procedure to optimise the comparator performance for a given N. First, a new configuration of the latch comparator has allowed optimising the comparison speed in terms of N. Second, the calibration scheme has been reduced to a simple digital sequencer to perform a progressive capacitive offset trimming. Third, the sequencer automatic increment has been programmed to stop at optimal operation to achieve the best calibration accuracy. The proposed method has then been applied to design a latch comparator with 7 bit calibration control in a commercially available 0.18 µm complementary metal–oxide–semiconductor technology. Post-layout statistical simulations have shown that the circuit can achieve up to 5.9 bit calibration resolution without altering the comparator performances.
Starting Page	726
Ending Page	734
Page Count	9
ISSN	1751858X
Volume Number	12
e-ISSN	17518598
Issue Number	Issue 6, Nov (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/12/6
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.5153
Journal	IET Circuits, Devices & Systems
Publisher Date	2018-09-14
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Calibration Calibration Accuracy Calibration Control Calibration Resolution Circuit Optimisation CMOS Integrated Circuit CMOS Logic Circuit Comparator Performance Comparators (circuits) Compensation Complementary Metal–oxide–semiconductor Technology Design Optimisation Procedure Digital Calibration Scheme Digital Circuit Design, Modelling And Testing Digital Mismatch Compensation Dynamic Comparators Flip Flops High-speed Operation Integrated Circuit Design Latch Comparator Layout Logic And Switching Circuit Logic Circuit Logic Design Method Low Power Electronics Modelling And Testing Post-layout Statistical Simulations Reduced Power Consumption Semiconductor Integrated Circuit Design Simple Digital Sequencer Size 0.18 Mum Three-step Design Procedure Word Length 5.9 Bit Word Length 7.0 Bit
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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