NDLI: Si3N4:HfO2 dual-k spacer bulk planar junctionless transistor for mixed signal integrated circuits

Content Provider	IET Digital Library
Author	Garike, Ramarao Patil, Ganesh C.
Abstract	For the first time halfnium oxide (HfO2) is being incorporated in the dual-k spacers and has been used in bulk planar junctionless transistor (BPJLT). It has been found that incorporating HfO2 in spacers not only improves the electrostatic integrity but also improves digital/analogue circuit performance of the BPJLT. Further, the increased effective gate length due to fringing electric field through HfO2 to thin body reduces OFF-state leakage, subthreshold swing and drain-induced barrier lowering by ∼60, ∼15 and ∼30%, respectively. Although the presence of HfO2 inner spacer layer at source/drain increases the parasitic capacitances, the significant improvement in ON-state drive current reduces the intrinsic gate delay of the device. Further, the analogue circuit figures of merit such as transconductance, transconductance generation factor and the intrinsic gain of the proposed device are found to be significantly improved over the conventional BPJLT device. The mixed mode device/circuit simulation results of an inverter and the common source amplifier show that leakage power dissipation, propagation delay and the open-circuit voltage gain of the proposed device are improved significantly over the conventional BPJLT device. The fabrication process flow of this novel device has also been proposed.
Starting Page	45
Ending Page	50
Page Count	6
ISSN	1751858X
Volume Number	13
e-ISSN	17518598
Issue Number	Issue 1, Jan (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/13/1
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2018.5168
Journal	IET Circuits, Devices & Systems
Publisher Date	2018-07-30
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Circuit Simulation Common Source Amplifier Conventional BPJLT Device Design And Testing Digital/analogue Circuit Performance Drain-induced Barrier Lowering Dual-k Spacer Bulk Planar Junctionless Transistor Electrostatic Integrity Equivalent Circuit Hafnium Compound Halfnium Oxide HfO2 Inner Spacer Layer Increased Effective Gate Length Insulated Gate Field Effect Transistors Intrinsic Gain Intrinsic Gate Delay Junctionless Nanowire Transistors Leakage Power Dissipation Mixed Analogue-digital Circuit Mixed Analogue-digital Integrated Circuit Mixed Mode Device/circuit Simulation Mixed Mode Device/circuit Simulation Result Mixed Signal Integrated Circuit OFF-state Leakage ON-state Drive Current Open-circuit Voltage Gain Semiconductor Device Model Semiconductor Device Modelling Si3N4:HfO2 Silicon Compound Source/drain Substhreshold Swing Transconductance Generation Factor
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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