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Noise measurement in high-speed domino pseudo-CMOS keeper

Content Provider	SAGE Publishing
Author	Jaikumar, R. Poongodi, P.
Copyright Year	2018
Abstract	Noise immunity is the foremost issue in high-speed domino circuits. In general, better noise immunity is achieved at the cost of speed and power degradation. In this paper, pseudo-dynamic keeper design is proposed to reduce the delay and power with improved noise immunity for domino circuits. The proposed technique is able to achieve reduced delay, power consumption, and better noise immunity by using always ON keeper. The simulation results show that the proposed technique exhibits 41%, 39%, and 19% delay reduction when compared with the low power dynamic circuit for two-input OR gate, two-input EX-OR gate, and 4:1 multiplexer. The proposed logic also performs better as compared to a low power dynamic circuit with 24%, 21%, and 14% reduction in power-delay product for two-input OR gate, two-input EX-OR gate, and four input MUX, respectively. The unity noise gain is also improved as compared to all other existing methods.
Related Links	https://journals.sagepub.com/doi/pdf/10.1177/0020294018813642?download=true
Starting Page	20
Ending Page	27
Page Count	8
ISSN	00202940
Issue Number	1-2
Volume Number	52
Journal	Measurement and Control (MAC)
DOI	10.1177/0020294018813642
Language	English
Publisher	Sage Publications UK
Publisher Date	2018-11-28
Publisher Place	London
Access Restriction	Open
Rights Holder	© The Author(s) 2018
Subject Keyword	power-delay product unity noise gain Noise-tolerant domino CMOS keeper charge sharing
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Control and Optimization Instrumentation

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