NDLI: Design approach to improve the performance of JAMFETs

Content Provider	IET Digital Library
Author	Raushan, Mohd Adil Alam, Naushad Siddiqui, Mohd Jawaid
Abstract	In this paper, the authors propose the use of electrostatic doping for n + drain region formation in Junctionless accumulation mode field effect transistors (JAMFET). This electrostatically doped drain (EDD) JAMFET employs an additional unbiased electrode (auxiliary electrode) of low workfunction on the intrinsic drain region. This technique effectively suppresses the tunneling leakage, thereby reducing I OFF by 6 orders. The tunneling of electrons from valence band of channel to conduction band of drain happens due to enhanced band bending in OFF-state (V GS = 0 V, V DS = 1 V). The presence of additional electrode in EDD-JAMFET increases the width of tunnel barrier formed at channel–drain junction in OFF-state improving the I ON/I OFF ratio by 6 orders. The gate length scaling demonstrates that leakage suppression of EDD-JAMFET is more effective with approximately 3 orders smaller I OFF even at gate length of 5 nm. The performance of graded channel device (GC-EDD-JAMFET) by electrostatic doping is also explored. Significant improvements are observed in terms of I ON/I OFF, subthreshold slope SS, DIBL and f T. Finally, the analogue parameters such as Transconductance generation factor G m/I D, Intrinsic gain A V, output conductance G D, and ‘G m/I D × f T’ performance metrics are investigated which show significant improvement at small bias current, making it suitable for ultra-low power applications.
Starting Page	333
Ending Page	339
Page Count	7
ISSN	1751858X
Volume Number	14
e-ISSN	17518598
Issue Number	Issue 3, May (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/14/3
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2019.0208
Journal	IET Circuits, Devices & Systems
Publisher Date	2020-01-13
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Additional Unbiased Electrode Channel–drain Junction Conduction Band Design And Testing Drain-induced Barrier Lowering Electrical/electronic Equipment Electrostatic Doping Electrostatically Doped Drain JAMFET Energy Utilisation Equivalent Circuit Field Effect Transistors Graded Channel Device Insulated Gate Field Effect Transistors Intrinsic Drain Region ION Junctionless Accumulation Mode Field-effect Transistors Junctionless Nanowire Transistors Low Power Electronics Matched P-type EDD-JAMFET MOSFET Performance Metrics Semiconductor Device Model Semiconductor Device Modelling Semiconductor Doping Size 5.0 Nm Small Bias Current Sub-threshold Slope Transconductance Generation Factor Tunnel Barrier Tunnelling Leakage Suppression Ultra-low Power Application Valence Band Voltage 0.0 V Work Function
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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