NDLI: Voltage-mode PAM4 driver with differential ternary R-2R DAC architecture

Content Provider	IET Digital Library
Author	Lim, B. Kim, D. H. Yoo, C.
Abstract	A voltage-mode pulse-amplitude modulation 4 (PAM4) driver with differential ternary R-2R DAC architecture is described. The differential ternary R-2R DAC provides three voltage levels with one R-2R branch, whereas the conventional one provides only two. Therefore, much less R-2R branches are required for a given number of output voltage levels. One of the three voltage levels is realised by simply short circuiting a differential input pair, saving power consumption. Implemented in 65 nm CMOS technology, the voltage-mode PAM4 driver occupies 0.073 mm2 active silicon area and consumes 1.97 mW/Gbit/s from 1.0 V supply at 10 Gbit/s.
Starting Page	431
Ending Page	432
Page Count	2
ISSN	00135194
Volume Number	56
e-ISSN	1350911X
Issue Number	Issue 9, Apr (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/56/9
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2019.3863
Journal	Electronics Letters
Publisher Date	2020-02-13
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	2 Active Silicon Area A/D And D/A Convertor Bit Rate 10.0 Gbit/s CMOS Integrated Circuit CMOS Technology Differential Input Pair Differential Ternary R-2R DAC Architecture Digital-analogue Conversion Driver Circuit Low Power Electronics Output Voltage Levels Power Consumption Power Electronics Power Supply Pulse Amplitude Modulation R-2R Branch Size 65 Nm Supervisory Circuit Voltage 1 V Voltage-mode PAM4 Driver Voltage-mode Pulse-amplitude Modulation 4 Driver
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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