NDLI: Impact of spintronic memory on multicore cache hierarchy design

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Impact of spintronic memory on multicore cache hierarchy design

Content Provider	IET Digital Library
Author	Ma, Cong Tuohy, William Lilja, David J.
Abstract	Spintronic memory [spin-transfer torque-magnetic random access memory (STT-MRAM)] is an attractive alternative technology to CMOS since it offers higher density and virtually no leakage current. Spintronic memory continues to require higher write energy, however, presenting a challenge to memory hierarchy design when energy consumption is a concern. This study motivates the use of STT-MRAM for the first-level caches of a multicore processor to reduce energy consumption without significantly degrading the performance. The large STT-MRAM first-level cache implementation saves leakage power. Moreover, the use of small level-0 cache regains the performance drop due to STT-MRAM long write latencies. The combination of both reduces the energy-delay product by 65% on average compared with CMOS baseline. The proposed STT hierarchy also shows good scalability over the CMOS with a few benchmarks which scale significantly better. The PARSEC and Splash2 benchmark suites are analysed running on a modern multicore platform, comparing performance, energy consumption and scalability of the spintronic cache system to a CMOS design.
Starting Page	51
Ending Page	59
Page Count	9
ISSN	17518601
Volume Number	11
e-ISSN	1751861X
Issue Number	Issue 2, Mar (2017)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cdt/11/2
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2015.0190
Journal	IET Computers & Digital Techniques
Publisher Date	2016-08-23
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Cache Storage Energy Consumption Magneto-acoustic Wave Device Magnetoresistive Wave Device Magnetostrictive And Magnetostatic Wave Device Memory Circuit MRAM Device Multicore Cache Hierarchy Design Multicore Processor Multiprocessing System PARSEC Semiconductor Storage Spin-transfer Torque-magnetic Random Access Memory Spintronic Memory Splash2 Storage Application STT-MRAM
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Software

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