NDLI: Recessed-channel reconfigurable field-effect transistor

Content Provider	IET Digital Library
Author	Kim, S. Kim, S. W.
Abstract	A new reconfigurable field-effect transistor (RFET) named as recessed-channel RFET (RC-RFET) is introduced herein to improve scalability, current drivability and subthreshold swing (S). There are two distinct features which allow RC-RFET to show enhanced performance than conventional RFET. First, a novel structure based RC and stacked gates increases effective channel length which results in suppressed short-channel-effect without any integration density penalty. Second, the switching mechanism of RC-RFET (thermionic emission) differs from that of conventional RFET (Schottky barrier tunnelling). It enables RC-RFET to overcome the fundamental limit of S degradation as a function of gate voltage and promises higher ON–OFF current ratio (I ON/I OFF) and its low-power applications. As a result, the RC-RFET shows I ON/I OFF higher than 107, small drain induced barrier lowering about 15 mV/V and ideal S (∼63 mV/decade) for 50 nm gate length.
Starting Page	1640
Ending Page	1642
Page Count	3
ISSN	00135194
Volume Number	52
e-ISSN	1350911X
Issue Number	Issue 19, Sep (2016)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/52/19
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2016.2401
Journal	Electronics Letters
Publisher Date	2016-08-25
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Channel Length Current Drivability Drain Induced Barrier Field Effect Device Field Effect Transistors Gate Voltage Low Power Electronics Low-power Application ON–OFF Current Ratio Performance Enhancement RC-RFET Recessed-channel Reconfigurable Field-effect Transistor Recessed-channel RFET Scalability Improvement Short-channel-effect Stacked Gate Structure Based RC Subthreshold Swing Thermionic Emission
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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