NDLI: Low-noise dynamic comparator circuit with selectable input-referred thermal noise voltage

Content Provider	IET Digital Library
Author	Yazid, M.
Abstract	A new method for reducing input-referred thermal noise of dynamic comparator circuit without increasing load capacitance as commonly used in the conventional method is proposed. An implementation circuit with selectable low-noise mode operation is presented, which enable both low-noise mode and standard mode operation by a single circuit. Simulation in 180 nm CMOS process technology shows that the proposed new method and circuit topology can achieve up to 90% increase in gain of comparator first stage, resulting in up to 40% decrease in input-referred thermal noise voltage, compared with a conventional circuit with similar load capacitance. The proposed circuit is also able to operate with similar performance as the conventional circuit when low-noise mode operation is not necessary.
Starting Page	1210
Ending Page	1212
Page Count	3
ISSN	00135194
Volume Number	54
e-ISSN	1350911X
Issue Number	Issue 21, Oct (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/54/21
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2018.5484
Journal	Electronics Letters
Publisher Date	2018-09-10
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Circuit Topology CMOS Integrated Circuit CMOS Logic Circuit CMOS Process Technology Comparator First Stage Comparators (circuits) Digital Circuit Digital Circuit Design, Modelling And Testing Flip Flops Input-referred Thermal Noise Voltage Load Capacitance Logic And Switching Circuit Logic Circuit Logic Design Method Low-noise Dynamic Comparator Circuit Low-noise Mode Operation Size 180 Nm Statistics Thermal Noise
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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