NDLI: Wide-input dynamic range 1 MHz clock ultra-low supply flip-flop

Content Provider	IET Digital Library
Author	Palaniappan, A. Ramaswami Siek, L.
Abstract	A new wide-input dynamic range flip-flop capable of operation at an ultra-low supply voltage of 0.16 V is presented. The proposed flip-flop named as capacitively boosted sense-amplifier flip-flop (CB-SAFF) utilises a capacitively boosted sense-amplifier master stage to sense the data signals and amplify them to a voltage higher than the supply and below the ground for driving the slave latch stage with improved strength. Using the same size of input/output transistors and load capacitance, the proposed CB-SAFF outperforms existing state-of-the-art sense-amplifier flip-flop designs at a low supply voltage operation from 0.16 to 0.6 V in terms of power delay product and clock to output propagation delay performance metrics. In addition, the proposed CB-SAFF can also sample low-swing data signals down to 0.2 V even at a 0.16 V supply voltage and 1 MHz clock frequency, thus making it highly suitable for applications that demand high speed and low power consumption such as for use in ultra-low voltage Internet of Things, wireless sensor nodes and smart motes.
Starting Page	938
Ending Page	939
Page Count	2
ISSN	00135194
Volume Number	54
e-ISSN	1350911X
Issue Number	Issue 15, Jul (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/54/15
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2018.1134
Journal	Electronics Letters
Publisher Date	2018-06-12
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Amplifiers Capacitively Boosted Sense-amplifier Flip-flop Capacitively Boosted Sense-amplifier Master Stage CB-SAFF Clock Frequency Clock to Output Propagation Delay Performance Metrics Clocks Digital Circuit Design, Modelling And Testing Flip Flops Frequency 1.0 MHz Input-output Transistors Load Capacitance Logic And Switching Circuit Logic Circuit Logic Design Method Low Power Consumption Low Power Electronics Low Supply Voltage Operation Power Delay Product Sample Low-swing Data Signal Sense-amplifier Flip-flop Designs Ultra-low Supply Voltage Voltage 0.16 V to 0.6 V Voltage 0.2 V Wide-input Dynamic Range Wide-input Dynamic Range Clock Ultra-low Supply Flip-flop
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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