NDLI: Highly digital 1 GS/s 7-bit PWM ADC in 65 nm CMOS using time-domain quantisation

Content Provider	IET Digital Library
Author	Saha, A. Harjani, R.
Abstract	A 2 × time-interleaved 1 GS/s 7b ADC is presented, which uses pulse-width modulation and time domain quantisation for digitisation and is designed for wide channel bandwidths available at mm-wave frequencies. The area, resolution and power performance of the highly digital time-domain architecture is likely to scale with technology. The prototype ADC achieves 5.24 ENOB at a Nyquist rate while consuming 5.22 mW of power, resulting in a FO M Walden , nyq = 138.13 fJ/conversion step in TSMC's 65 nm GP CMOS process.
Starting Page	1204
Ending Page	1206
Page Count	3
ISSN	00135194
Volume Number	54
e-ISSN	1350911X
Issue Number	Issue 21, Oct (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/54/21
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2018.5393
Journal	Electronics Letters
Publisher Date	2018-09-12
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	A/D And D/A Convertor Analogue-Digital Conversion CMOS Digital Integrated Circuit CMOS Integrated Circuit Digital Circuit Design, Modelling And Testing Logic Design Method Mm-wave Frequency Nyquist Rate Power 5.22 MW Pulse Width Modulation PWM ADC Size 65 Nm Time Domain Analysis Time Domain Quantisation Time-domain Quantisation Time-interleaved ADC TSMC GP CMOS Process Wide Channel Bandwidths
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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Highly digital 1 GS/s 7-bit PWM ADC in 65 nm CMOS using time-domain quantisation